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IEICE TRANSACTIONS on Electronics
0.48 1.3
Volume E78-C No.7  (Publication Date:1995/07/25)
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Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age

pp.765-765  FOREWORD
FOREWORD
Masahide TAKADA  
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pp.766-772  INVITED PAPER
ULSI Memory for Multimedia Applications
Yasuo AKATSUKA  Yoichi YANO  Shigeo NIITSU  Akihiko MORINO  
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pp.773-781  INVITED PAPER
Emerging Memory Solutions for Graphics Applications
Katsumi SUIZU  Toshiyuki OGAWA  Kazuyasu FUJISHIMA  
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pp.782-788  PAPER
A Synchronous DRAM with New High-Speed I/O Lines Method for the MultiMedia Age
Yuji SAKAI  Kanji OISHI  Miki MATSUMOTO  Shoji WADA  Tadamichi SAKASHITA  Masahiro KATAYAMA  
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pp.789-796  PAPER
NAND-Structured Trench Capacitor Cell Technologies for 256 Mb DRAM and Beyond
Takeshi HAMAMOTO  Yutaka ISHIBASHI  Masami AOKI  Yoshihiko SAITOH  Takashi YAMADA  
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pp.797-804  PAPER
A Low-Power Synchronous SRAM Macrocell with Latch-Type Fast Sense Circuits
Nobutaro SHIBATA  Mayumi WATANABE  
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pp.805-811  PAPER
PLL Timing Design Techniques for Large-Scale, High-Speed, Low-Power, Low-Cost SRAMs
Kazuyuki NAKAMURA  Shigeru KUHARA  Thoru KIMURA  Masahide TAKADA  Hisamitsu SUZUKI  Hiroshi YOSHIDA  Tohru YAMAZAKI  
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pp.812-817  PAPER
Low-Voltage Operation of a High-Resistivity Load SOI SRAM Cell by Reduced Back-Gate-Bias Effect
Yasuo YAMAGUCHI  Jun TAKAHASHI  Takehisa YAMAGUCHI  Tomohisa WADA  Toshiaki IWAMATSU  Hans-Oliver JOACHIM  Yasuo INOUE  Tadashi NISHIMURA  Natsuro TSUBOUCHI  
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pp.818-824  PAPER
A 65 ns 3 V-only NAND-Flash Memory with New Verify Scheme and Folded Bit-Line Architecture
Hiromi NOBUKATA  Kenichi SATORI  Shinji HIRAMATSU  Hideki ARAKAWA  
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pp.825-831  PAPER
Design of a 3.3 V Single Power-Supply 64 Mbit Flash Memory with Dynamic Bit-Line Latch (DBL) Programming Scheme
Hiroshi SUGAWARA  Toshio TAKESHIMA  Hiroshi TAKADA  Yoshiaki S. HISAMUNE  Kohji KANAMORI  Takeshi OKAZAWA  Tatsunori MUROTANI  Isao SASAKI  
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pp.832-837  PAPER
Programming and Program-Verification Methods for Low-Voltage Flash Memories Using a Sector Programming Scheme
Katsutaka KIMURA  Toshihiro TANAKA  Masataka KATO  Tetsuo ADACHI  Keisuke OGURA  Hitoshi KUME  
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pp.838-844  PAPER
BIST Circuit Macro Using Microprogram ROM for LSI Memories
Hiroki KOIKE  Toshio TAKESHIMA  Masahide TAKADA  
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pp.845-851  PAPER
New α-Particle Induced Soft Error Mechanism in a Three Dimensional Capacitor Cell
Yukihito OOWAKI  Keiji MABUCHI  Shigeyoshi WATANABE  Kazunori OHUCHI  Jun'ichi MATSUNAGA  Fujio MASUOKA  
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pp.852-857  PAPER
Use of a Monte Carlo Wiring Yield Simulator to Optimize Design of Random Logic Circuits for Yield Enhancement
Hideyuki FUKUHARA  Takao KOMATSUZAKI  Katsushi BOKU  Yoichi MIYAI  
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Regular Section

pp.858-865  PAPER-Integrated Electronics
Fully Self-Timing Data-Bus Architecture for 64-Mb DRAMs
Tadaaki YAMAUCHI  Koji TANAKA  Kiyohiro FURUTANI  Yoshikazu MOROOKA  Hiroshi MIYAMOTO  Hideyuki OZAKI  
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pp.866-872  PAPER-Integrated Electronics
3.0 Gb/s, 272 mW, 8:1 Multiplexer and 4.1 Gb/s, 388 mW, 1:8 Demultiplexer
Kimio UEDA  Nagisa SASAKI  Hisayasu SATO  Shunji KUBO  Koichiro MASHIKO  
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pp.873-877  PAPER-Superconductive Electronics
Frequency-Dependent Finite-Difference Time-Domain Analysis of High-Tc Superconducting Asymmetric Coplanar Strip Line
Masafumi HIRA  Yasunobu MIZOMOTO  Sadao KURAZONO  
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pp.878-884  PAPER-Electronic Displays
Analysis on Reduction of the Temperature Rise of Deflection Yoke (DY)
Rensi MOROOKA  Yukitoshi INOUE  Katsuhiko SHIOMI  
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pp.885-886  LETTER-Opto-Electronics
Fiber Optic Temperature Sensor Using Two Modes by Holographic Filter
Manabu YOSHIKAWA  Kazuo ASAKAWA  
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