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IEICE TRANSACTIONS on Electronics
0.35 1.3
Volume E78-C No.6  (Publication Date:1995/06/25)
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Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995)

pp.587-588  FOREWORD
FOREWORD
Kevin J. O'CONNOR  Atsushi IWATA  
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pp.589-595  PAPER
ATM in B-ISDN Communication Systems and VISI Realization
Takeo KOINUMA  Noriharu MIYAHO  
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pp.596-600  PAPER
Asynchronous Transfer Mode Switching LSI Chips with 10-Gb/s Serial I/O Ports
Shigeki HINO  Minoru TOGASHI  Kimiyoshi YAMASAKI  
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pp.601-612  PAPER
A CMOS Serial Link for Fully Duplexed Data Communication
Kyeongho LEE  Sungjoon KIM  Gijung AHN  Deog-Kyoon JEONG  
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pp.613-618  PAPER
A 256-Element Associative Parallel Processor
Frederick P. HERRMANN  Charles G. SODINI  
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pp.619-622  PAPER
Future Directions in Microprocessor Technology
Maurice P. MARKS  
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pp.623-630  PAPER
Cache-Processor Coupling: A Fast and Wide On-Chip Data Cache Design
Masato MOTOMURA  Toshiaki INOUE  Hachiro YAMADA  Akihiko KONAGAYA  
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pp.631-639  PAPER
A Wide-Bandwidth Low-Voltage PLL for PowerPCTM Microprocessors
Jose ALVAREZ  Hector SANCHEZ  Gianfranco GEROSA  Roger COUNTRYMAN  
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pp.640-644  PAPER
A Multiplexer-Based Architecture for High-Density, Low-Power Gate Arrays
Robert J. LANDERS  Shivaling S. MAHANT-SHETTI  Carl LEMONDS  
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pp.645-650  PAPER
Data-Dependent Logic Swing Internal Bus Architecture for Ultralow-Power LSI's
Mitsuru HIRAKI  Hirotsugu KOIJIMA  Hitoshi MISAWA  Takashi AKAZAWA  Yuji HATANO  
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pp.651-659  PAPER
A Programmable Clock Generator that Uses Noise Shaping and Its Application in Switched-Capacitor Filters
Paul J. HURST  Bret C. ROTHENBERG  
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pp.660-670  PAPER
An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessors
Jim DUNNING  Gerald GARCIA  Jim LUNDBERG  Ed NUCKOLLS  
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pp.671-679  PAPER
An Asymptotically Zero Power Charge-Recycling Bus Architecture for Battery-Operated Ultrahigh Data Rate ULSI'S
Hiroyuki YAMAUCHI  Hironori AKAMATSU  Tsutomu FUJITA  
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pp.680-683  PAPER
Half-Swing Clocking Scheme for 75% Power Saving in Clocking Circuitry
Hirotsugu KOJIMA  Satoshi TANAKA  Katsuro SASAKI  
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pp.684-690  PAPER
Present and Future Directions for Multichip Module Technologies
Toshio SUDO  
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pp.691-700  PAPER
A 13-b 10-Msample/s ADC Digitally Calibrated with Oversampling Delta-Sigma Converter
Tzi-Hsiung SHU  Bang-Sup SONG  Kantilal BACRANIA  
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pp.701-708  PAPER
A High Resolution Multibit Sigma-Delta Modulator with Individual Level Averaging
Feng CHEN  Bosco H. LEUNG  
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pp.709-718  PAPER
A Median Peak Detecting Analog Signal Processor for Hard Disk Drive Servo
Krhishnaswamy NAGARAJ  Stephen H. LEWIS  Robert W. WALDEN  Glen E. OFFORD  Reza S. SHARIATDOUST  Jyoti A. SABNIS  Robert O. PERUZZI  Jeffrey R. BARNER  Joseph PLANY  Robert P. MENTO  Vafa A. RAKSHANI  Richard W. HULL  
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pp.719-727  PAPER
An Automatic Temperature Compensation of Internal Sense Ground for Subquarter Micron DRAM's
Tsukasa OOISHI  Yuichiro KOMIYA  Kei HAMADE  Mikio ASAKURA  Kenichi YASUDA  Kiyohiro FURUTANI  Hideto HIDAKA  Hiroshi MIYAMOTO  Hideyuki OZAKI  
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pp.728-734  PAPER
A 6-ns 4-Mb CMOS SRAM with Offset-Voltage-Insensitive Current Sense Amplifiers
Koichiro ISHIBASHI  Koichi TAKASUGI  Kunihiro KOMIYAJI  Hiroshi TOYOSHIMA  Toshiaki YAMANAKA  Akira FUKAMI  Naotaka HASHIMOTO  Nagatoshi OHKI  Akihiro SHIMIZU  Takashi HASHIMOTO  Takahiro NAGANO  Takashi NISHIDA  
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pp.735-738  PAPER
A 2.6-ns Wave-Pipelined CMOS SRAM with Dual-Sensing-Latch Circuits
Suguru TACHIBANA  Hisayuki HIGUCHI  Koichi TAKASUGI  Katsuro SASAKI  Toshiaki YAMANAKA  Yoshinobu NAKAGOME  
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pp.739-747  PAPER
A 0.65-ns, 72-kb ECL-CMOS RAM Macro for a 1-Mb SRAM
Hiroaki NAMBU  Kazuo KANETANI  Youji IDEI  Toru MASUDA  Keiichi HIGETA  Masayuki OHAYASHI  Masami USAMI  Kunihiko YAMAGUCHI  Toshiyuki KIKUCHI  Takahide IKEDA  Kenichi OHHATA  Takeshi KUSUNOKI  Noriyuki HOMMA  
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pp.748-759  PAPER
A Source Sensing Technique Applied to SRAM Cells
Kevin J. O'CONNOR  
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