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IEICE TRANSACTIONS on Electronics
0.35 1.3
Volume E74-C No.11  (Publication Date:1991/11/25)
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Special Issue on the High Performance ASIC and Microprocessor

pp.3747-3748  FOREWORD
FOREWORD
Osamu TOMISAWA  
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pp.3749-3756  PAPER-Circuit Design
A Master Chip Design of 0.5 µm Mixed BiCMOS/CMOS Channelless Gate Array Family
Yoji NISHIO  Noriaki OKA  Shigeru TAKAHASHI  Manabu SHIBATA  
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pp.3757-3765  PAPER-Circuit Design
Self-Timed Clocking Design for a Data-Driven Microprocessor
Fumiyasu ASAI  Shinji KOMORI  Toshiyuki TAMURA  Hisakazu SATO  Hidehiro TAKATA  Yoshihiro SEGUCHI  Takeshi TOKUDA  Hiroaki TERADA  
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pp.3766-3774  PAPER-Core and Macrocells
A High Performance 32-Bit Microcontroller for Realtime Applications
Masafumi TAKAHASHI  Yasuo YAMADA  Emi KANEKO  Shinichi YOSHIOKA  Haruyuki TAGO  
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pp.3775-3779  PAPER-Core and Macrocells
A 64 b CMOS Mainframe Execution Unit Macrocell with Error Detecting Circuit
Takehisa HAYASHI  Toshio DOI  Mikio YAMAGISHI  Kazuo KOIDE  Akira ISHIYAMA  Masataka HIRAMATSU  Akira YAMAGIWA  
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pp.3780-3786  PAPER-Core and Macrocells
A 5 ns Embedded RAM for CMOS ASICs and Its Applications to a One-Chip 4096-Channel Time Switch VLSI for Digital Switching Systems
Masao MIZUKAMI  Yasuo MIKAMI  Osamu MATSUBARA  Yoichi SATOH  Koichi SUDOH  
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pp.3787-3795  PAPER-Core and Macrocells
A High-Performance Reconfigurable Line Memory Macrocell for Video Signal Processing ASICs
Tetsuya MATSUMURA  Masahiko YOSHIMOTO  Atsushi MAEDA  Yasutaka HORIBA  
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pp.3796-3802  PAPER-System VLSI
An Intelligent Cache Memory Chip Suitable for Logical Inference
Kenichi YASUDA  Kiyohiro FURUTANI  Atsushi MAEDA  Shoichi WAKANO  Hiroshi NAKASHIMA  Yasutaka TAKEDA  Michihiro YAMADA  
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pp.3803-3809  PAPER-System VLSI
The Performance Evaluation of a 64 b Microprocessor with a Two-Level Cache
Ryuichi YAMAGUCHI  Joel BONEY  Douglas DUSCHATKO  Tetsuya TANAKA  Jiro MIYAKE  Yoshito NISHIMICHI  Hisakazu EDAMATSU  Shigeru WATARI  Shigeo KUNINOBU  
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pp.3810-3818  PAPER-System VLSI
VLSI Implementation of a Parallel Computer Network
Katsuyuki KANEKO  Ichiro OKABAYASHI  Shingo KARINO  Yasuhiro NAKAKURA  Tetsuji KISHI  Manabu MIGITA  
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pp.3819-3828  PAPER-Dedicated Processors
Design of a Matrix Multiply-Addition VLSI Processor for Robot Inverse Dynamics Computation
Somchai KITTICHAIKOONKIT  Michitaka KAMEYAMA  Tatsuo HIGUCHI  
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pp.3829-3837  PAPER-Dedicated Processors
A Special-Purpose LSI for Inverse Kinematics Computation
Michitaka KAMEYAMA  Takao MATSUMOTO  Hideki EGAMI  Tatsuo HIGUCHI  
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pp.3838-3844  PAPER-Dedicated Processors
Built-In Self-Test in a 24 Bit Floating Point Digital Signal Processor
Narumi SAKASHITA  Hisako SAWAI  Eiichi TERAOKA  Toshiki FUJIYAMA  Tohru KENGAKU  Yukihiko SHIMAZU  Akiharu TADA  Takeshi TOKUDA  
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pp.3845-3851  PAPER-Dedicated Processors
A 400 MFLOPS FFT Processor VLSI Architecture
Hiroshi MIYANAGA  Hironori YAMAUCHI  
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pp.3852-3860  PAPER-Dedicated Processors
Architecture of a Floating-Point Butterfly Execution Unit in a 400-MFLOPS Processor VLSI and Its Implementation
Hironori YAMAUCHI  Hiroshi MIYANAGA  
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Regular Section

pp.3861-3866  PAPER-Opto-Electronics
Ni-Plated Anodic Alumina Film for Optical Polarizer
Takashi SEKI  Mitsunori SAITO  Mitsunobu MIYAGI  
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pp.3867-3869  LETTER-Opto-Electronics
Temperature Characteristics of Short-Cavity AIGaAs/GaAs Surface Emitting Lasers
Takemasa TAMANUKI  Kazuhiko HOUJOU  Fumio KOYAMA  Kenichi IGA  
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pp.3870-3872  LETTER-Opto-Electronics
Effect of Annealing on Electrooptic Constant of the Undoped and the MgO-Doped Lithium Niobate Optical Waveguides
Thi Thi LAY  Yukiko KONDO  Yoichi FUJII  
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