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IEICE TRANSACTIONS on Electronics
Volume E87-C No.4  (Publication Date:2004/04/01)
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Special Section on Low-Power System LSI, IP and Related Technologies

pp.427-428  FOREWORD
FOREWORD
Masahiko YOSHIMOTO  
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pp.429-436  INVITED PAPER
Perspectives of Low-Power VLSI's
Takayasu SAKURAI  
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pp.437-447  INVITED PAPER
Ultralow-Voltage MTCMOS/SOI Circuits for Batteryless Mobile System
Takakuni DOUSEKI  Masashi YONEMARU  Eiji IKUTA  Akira MATSUZAWA  Atsushi KAMEYAMA  Shunsuke BABA  Tohru MOGAMI  Hakaru KYURAGI  
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pp.448-456  PAPER
A Single-Chip JPEG2000 Encode Processor Capable of Compressing D1-Images at 30 frames/s without Tile Division
Hideki YAMAUCHI  Shigeyuki OKADA  Kazuhiko TAKETA  Tatsushi OHYAMA  
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pp.457-465  PAPER
A Feed-Forward Dynamic Voltage Control Algorithm for Low Power MPEG4 on Multi-Regulated Voltage CPU
Hideo OHIRA  Kentaro KAWAKAMI  Miwako KANAMORI  Yasuhiro MORITA  Masayuki MIYAMA  Masahiko YOSHIMOTO  
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pp.466-474  PAPER
VLSI-Oriented Motion Estimation Using a Steepest Descent Method in Mobile Video Coding
Masayuki MIYAMA  Junichi MIYAKOSHI  Kousuke IMAMURA  Hideo HASHIMOTO  Masahiko YOSHIMOTO  
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pp.475-481  PAPER
A 160 mW, 80 nA Standby, MPEG-4 Audiovisual LSI with 16 Mbit Embedded DRAM and a 5 GOPS Post Filtering Unit
Hideho ARAKIDA  Masafumi TAKAHASHI  Yoshiro TSUBOI  Tsuyoshi NISHIKAWA  Hideaki YAMAMOTO  Toshihide FUJIYOSHI  Yoshiyuki KITASHO  Yasuyuki UEDA  Tetsuya FUJITA  
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pp.482-490  PAPER
A Single Chip H.32X Multimedia Communication Processor with CIF 30 fr/s MPEG-4/H.26X Bi-directional Codec
Noriyuki MINEGISHI  Ken-ichi ASANO  Keisuke OKADA  Masahiko YOSHIMOTO  
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pp.491-501  PAPER
A 1.5 V, 200 MHz, 400 MIPS, 188 µA/MHz and 1.2 V, 300 MHz, 600 MIPS, 169 µA/MHz Digital Signal Processor Core for 3G Wireless Applications
Hiroshi TAKAHASHI  Shigeshi ABIKO  Kenichi TASHIRO  Kaoru AWAKA  Yutaka TOYONOH  Rimon IKENO  Shigetoshi MURAMATSU  Yasumasa IKEZAKI  Tsuyoshi TANAKA  Akihiro TAKEGAMA  Hiroshi KIMIZUKA  Hidehiko NITTA  Miki KOJIMA  Masaharu SUZUKI  James Lowell LARIMER  
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pp.502-509  PAPER
A 100 MHz 7.84 mm2 31.7 msec 439 mW 512-Point 2-Dimensional FFT Single-Chip Processor
Naoto MIYAMOTO  Leo KARNAN  Kazuyuki MARUO  Koji KOTANI  Tadahiro OHMI  
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pp.510-519  PAPER
A Low Power Programmable Turbo Decoder Macro Using the SOVA Algorithm
Hirohisa GAMBE  Kazuhisa OHBUCHI  Teruo ISHIHARA  Takaaki ZAKOJI  Kiyomichi ARAKI  
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pp.520-526  PAPER
A Physical Synthesis Methodology for Multi-Threshold-Voltage Design in Low-Power Embedded Processor
Toshihiro HATTORI  Kenji OGURA  
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pp.527-534  PAPER
Design of a Fast Asynchronous Embedded CISC Microprocessor, A8051
Je-Hoon LEE  YoungHwan KIM  Kyoung-Rok CHO  
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pp.535-542  PAPER
Selective-Sets Resizable Cache Memory Design for High-Performance and Low-Power CPU Core
Takashi KURAFUJI  Yasunobu NAKASE  Hidehiro TAKATA  Yukinaga IMAMURA  Rei AKIYAMA  Tadao YAMANAKA  Atsushi IWABU  Shutarou YASUDA  Toshitsugu MIWA  Yasuhiro NUNOMURA  Niichi ITOH  Tetsuya KAGEMOTO  Nobuharu YOSHIOKA  Takeshi SHIBAGAKI  Hiroyuki KONDO  Masayuki KOYAMA  Takahiko ARAKAWA  Shuhei IWADE  
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pp.543-548  PAPER
A Novel Static Prediction Scheme for Filter Cache Structures
Kugan VIVEKANANDARAJAH  Thambipillai SRIKANTHAN  Christopher T. CLARKE  Saurav BHATTACHARYYA  
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pp.549-555  PAPER
Electric-Energy Generation through Variable-Capacitive Resonator for Power-Free LSI
Masayuki MIYAZAKI  Hidetoshi TANAKA  Goichi ONO  Tomohiro NAGANO  Norio OHKUBO  Takayuki KAWAHARA  
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pp.556-562  PAPER
A Full-CMOS Single Chip Bluetooth LSI with 1.5 MHz-IF Receiver and Direct Modulation Transmitter
Fumitoshi HATORI  Hiroki ISHIKURO  Mototsugu HAMADA  Ken-ichi AGAWA  Shouhei KOUSAI  Hiroyuki KOBAYASHI  Duc Minh NGUYEN  
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pp.563-570  PAPER
A Low-Power Microcontroller with Body-Tied SOI Technology
Hisakazu SATO  Yasuhiro NUNOMURA  Niichi ITOH  Koji NII  Kanako YOSHIDA  Hironobu ITO  Jingo NAKANISHI  Hidehiro TAKATA  Yasunobu NAKASE  Hiroshi MAKINO  Akira YAMADA  Takahiko ARAKAWA  Toru SHIMIZU  Yuichi HIRANO  Takashi IPPOSHI  Shuhei IWADE  
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pp.571-577  PAPER
A Wide Range 1.0-3.6 V 200 Mbps, Push-Pull Output Buffer Using Parasitic Bipolar Transistors
Takahiro SHIMADA  Hiromi NOTANI  Yasunobu NAKASE  Hiroshi MAKINO  Shuhei IWADE  
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pp.578-581  PAPER
+3 V/-3 V Operation 1.2 Gbps Write Driver for Hard Disk Drives
Yasuyuki OKUMA  Kenji MAIO  Hiroyasu YOSHIZAWA  
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pp.582-588  PAPER
Low-Power Multiple-Valued Current-Mode Logic Using Substrate Bias Control
Akira MOCHIZUKI  Takahiro HANYU  
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pp.589-597  PAPER
µI/O Architecture: A Power-Aware Interconnect Circuit Design for SoC and SiP
Yusuke KANNO  Hiroyuki MIZUNO  Nobuhiro OODAIRA  Yoshihiko YASU  Kazumasa YANAGISAWA  
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pp.598-605  PAPER
A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits
Masanori MUROYAMA  Akihiko HYODO  Takanori OKUMA  Hiroto YASUURA  
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pp.606-612  PAPER
Memory Data Organization for Low-Energy Address Buses
Hiroyuki TOMIYAMA  Hiroaki TAKADA  Nikil D. DUTT  
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pp.613-620  PAPER
Circuit Partition and Reordering Technique for Low Power IP Design
Kun-Lin TSAI  Shanq-Jang RUAN  Chun-Ming HUANG  Edwin NAROSKA  Feipei LAI  
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pp.621-628  PAPER
A Design for Testability Technique for Low Power Delay Fault Testing
James Chien-Mo LI  
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pp.629-633  LETTER
Pipelined Wake-Up Scheme to Reduce Power Line Noise for Block-Wise Shutdown of Low-Power VLSI Systems
Jin-Hyeok CHOI  Yong-Ju KIM  Jae-Kyung WEE  Seongsoo LEE  
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Regular Section

pp.634-639  PAPER-Electronic Circuits
A Low Power and Small Area Analog Adaptive Line Equalizer for 100 Mb/s Data Rate on UTP Cable
Kwisung YOO  Hoon LEE  Gunhee HAN  
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pp.640-644  LETTER-Electronic Circuits
A Low-Power Edge-Triggered and Logic-Embedded Flip-Flop Using Complementary Pass Transistor Circuit
Ki-Tae PARK  Tomokatsu MIZUKUSA  Hyo-Sig WON  Hiroyuki KURINO  Mitsumasa KOYANAGI  
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pp.645-648  LETTER-Electronic Circuits
A Power-Down Circuit Scheme Using Data-Preserving Complementary Pass Transistor Flip-Flop for Low-Power High-Performance Multi-Threshold CMOS LSI
Ki-Tae PARK  Tomokatsu MIZUKUSA  Hyo-Sig WON  Kyu-Myung CHOI  Jeong-Taek KONG  Hiroyuki KURINO  Mitsumasa KOYANAGI  
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