IEICE Trans

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences

Volume E84-A No.11 (Publication Date:2001/11/01)

Special Section on VLSI Design and CAD Algorithms

pp.2613-2613 FOREWORD FOREWORD Hidetoshi ONODERA
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pp.2614-2622 PAPER-VLSI Design System-MSPA Design of H.263+ Video Encoder/Decoder LSI for Videotelephony Applications Chawalit HONSAWEK Kazuhito ITO Tomohiko OHTSUKA Trio ADIONO Dongju LI Tsuyoshi ISSHIKI Hiroaki KUNIEDA
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pp.2623-2631 PAPER-VLSI Design Design of High-Radix VLSI Dividers without Quotient Selection Tables Takafumi AOKI Kimihiko NAKAZAWA Tatsuo HIGUCHI
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pp.2632-2638 PAPER-IP Protection Hierarchical Intellectual Property Protection Using Partially-Mergeable Cores Vikram IYENGAR Hiroshi DATE Makoto SUGIHARA Krishnendu CHAKRABARTY
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pp.2639-2647 PAPER-Hardware/Software Codesign Area and Delay Estimation in Hardware/Software Cosynthesis for Digital Signal Processor Cores Nozomu TOGAWA Yoshiharu KATAOKA Yuichiro MIYAOKA Masao YANAGISAWA Tatsuo OHTSUKI
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pp.2648-2654 PAPER-High Level Synthesis An RTL Design-Space Exploration Method for High-Level Applications Peng-Cheng KAO Chih-Kuang HSIEH Ching-Feng SU Allen C.-H. WU
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pp.2655-2664 PAPER-High Level Synthesis High-Level Synthesis of Pipelined Circuits from Modular Queue-Based Specifications Maria-Cristina MARINESCU Martin RINARD
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pp.2665-2672 PAPER-Logic Synthesis Generalized Reasoning Scheme for Redundancy Addition and Removal Jose Alberto ESPEJO Luis ENTRENA Enrique San MILLAN Celia LOPEZ
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pp.2673-2680 PAPER-Logic Synthesis Timing Driven Gate Duplication in Technology Independent Phase Ankur SRIVASTAVA Chunhong CHEN Majid SARRAFZADEH
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pp.2681-2689 PAPER-FPGA Systhesis LUT-Array-Based PLD and Synthesis Approach Based on Sum of Generalized Complex Terms Expression Hiroshi TSUTSUI Akihiko TOMITA Shigenori SUGIMOTO Kazuhisa SAKAI Tomonori IZUMI Takao ONOYE Yukihiro NAKAMURA
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pp.2690-2696 PAPER-FPGA Systhesis A Routability Driven Technology Mapping Algorithm for LUT Based FPGA Designs Chi-Chou KAO Yen-Tai LAI
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pp.2697-2704 PAPER-Layout VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation Yuchun MA Xianlong HONG Sheqin DONG Yici CAI Chung-Kuan CHENG Jun GU
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pp.2705-2713 PAPER-Layout A Practical Clock Tree Synthesis for Semi-Synchronous Circuits Keiichi KUROKAWA Takuya YASUI Masahiko TOYONAGA Atsushi TAKAHASHI
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pp.2714-2721 PAPER-Layout Reducing Wire Lengths in the Layout of Cyclic Shifters Peter-Michael SEIDEL Mark A. HILLEBRAND Thomas SCHURGER
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pp.2722-2730 PAPER-Test Novel DFT Strategies Using Full/Partial Scan Designs and Test Point Insertion to Reduce Test Application Time Toshinori HOSOKAWA Masayoshi YOSHIMURA Mitsuyasu OHTA
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pp.2731-2738 PAPER-Test Optimization of Test Accesses with a Combined BIST and External Test Scheme Makoto SUGIHARA Hiroto YASUURA
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pp.2739-2745 PAPER-Timing Analysis Robust Performance Optimization Using Padding Nodes and Separator Sets Yutaka TAMIYA
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pp.2746-2754 PAPER-Timing Analysis An Algorithm for Statistical Static Timing Analysis Considering Correlations between Delays Shuji TSUKIYAMA Masakazu TANAKA Masahiro FUKUI
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pp.2755-2761 PAPER-Optimization of Power and Timing A System Level Optimization Technique for Application Specific Low Power Memories Tohru ISHIHARA Kunihiro ASADA
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pp.2762-2768 PAPER-Optimization of Power and Timing Reducing Cache Energy Dissipation by Using Dual Voltage Supply Vasily G. MOSHNYAGA Hiroshi TSUJI
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pp.2769-2777 PAPER-Optimization of Power and Timing Post-Layout Transistor Sizing for Power Reduction in Cell-Base Design Masanori HASHIMOTO Hidetoshi ONODERA
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pp.2778-2784 PAPER-Analog Design Analog Circuit Synthesis Based on Reuse of Topological Features of Prototype Circuits Hajime SHIBATA Nobuo FUJII
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pp.2785-2792 PAPER-Analog Design Using Non-slicing Topological Representations for Analog Placement Florin BALASA Sarat C. MARUVADA
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pp.2793-2801 PAPER-Analog Design A Dynamically Phase Adjusting PLL for Improvement of Lock-up Performance Takeo YASUDA Hiroaki FUJITA Hidetoshi ONODERA
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pp.2802-2807 LETTER-Hardware/Software Codesign A New Hardware/Software Partitioning Algorithm for DSP Processor Cores with Two Types of Register Files Nozomu TOGAWA Takashi SAKURAI Masao YANAGISAWA Tatsuo OHTSUKI
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pp.2808-2810 LETTER-Analog Synthesis Evolutionary Graph Generation System with Terminal-Color Constraint--An Application to Multiple-Valued Logic Circuit Synthesis-- Masanori NATSUI Takafumi AOKI Tatsuo HIGUCHI
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Special Section on Concurrent Systems Technology

pp.2811-2811 FOREWORD FOREWORD Haruo HASEGAWA
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pp.2812-2821 INVITED PAPER Enhancing Software Project Simulator toward Risk Prediction with Cost Estimation Capability Osamu MIZUNO Daisuke SHIMODA Tohru KIKUNO Yasunari TAKAGI
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pp.2822-2828 PAPER Weak Normality for Nonblocking Supervisory Control of Discrete Event Systems under Partial Observation Shigemasa TAKAI Toshimitsu USHIO
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pp.2829-2837 PAPER A Petri-Net-Based Model for the Mathematical Analysis of Multi-Agent Systems Kunihiko HIRAISHI
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pp.2838-2851 PAPER A Computation Method of LSN for Extended 2-b-SPGs Qi-Wei GE Yasunori SUGIMOTO
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pp.2852-2864 PAPER Performance Evaluation on Transient Time of Dynamic Workflow Changes Shingo YAMAGUCHI Yuko SHIODE Qi-Wei GE Minoru TANAKA
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pp.2865-2870 PAPER Polynomial Time Decidability of Monotone Liveness of Time Bounded AC/DC Nets Atsushi OHTA Kohkichi TSUJI
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pp.2871-2880 PAPER Experimental Evaluation of Two Algorithms for Computing Petri Net Invariants Katsushi TAKANO Satoshi TAOKA Masahiro YAMAUCHI Toshimasa WATANABE
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pp.2881-2884 LETTER An Algorithm for Legal Firing Sequence Problem of Petri Nets Based on Partial Order Method Kunihiko HIRAISHI Hirohide TANAKA
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Regular Section

pp.2885-2893 PAPER-Digital Signal Processing Novel VLIW Code Compaction Method for a 3D Geometry Processor Hiroaki SUZUKI Hiroyuki KAWAI Hiroshi MAKINO Yoshio MATSUDA
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pp.2894-2900 PAPER-Digital Signal Processing On the Frequency Estimation of Signal by Using the Expansion of LP Method in the Noisy Circumstance Yongmei LI Kazunori SUGAHARA Tomoyuki OSAKI Ryosuke KONISHI
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pp.2901-2907 PAPER-Systems and Control A Design of Generalized Minimum Variance Controllers Using a GMDH Network for Nonlinear Systems Akihiro SAKAGUCHI Toru YAMAMOTO
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pp.2908-2914 PAPER-Nonlinear Problems Chaotic Multidomain Oscillations in a Spatially-Extended Semiconductor Device Hidetaka ITO Yoshisuke UEDA
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pp.2915-2922 PAPER-VLSI Design Technology and CAD A General Framework to Use Various Decomposition Methods for LUT Network Synthesis Shigeru YAMASHITA Hiroshi SAWADA Akira NAGOYA
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pp.2923-2929 PAPER-Reliability, Maintainability and Safety Analysis K-Terminal Reliability of FDDI Ring Network with a Constrained Number of Consecutively Bypassed Stations Kyung Soo PARK Gue Woong JUNG
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pp.2930-2938 PAPER-Information Security Construction of Secure C_ab Curves Using Modular Curves Seigo ARITA
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pp.2939-2945 PAPER-Coding Theory Instantaneously Reversible Golomb-Rice Codes for Robust Image Coding Muling GUO Madoka HASEGAWA Shigeo KATO Juichi MIYAMICHI
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pp.2946-2949 LETTER-Digital Signal Processing Amplitude Banded RLS Approach to Time Variant Channel Equalization Tetsuya SHIMAMURA Colin F. N. COWAN
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pp.2950-2952 LETTER-Nonlinear Problems Finding All Solutions of Nonlinear Equations Using Inverses of Approximate Jacobian Matrices Kiyotaka YAMAMURA Takayoshi KUMAKURA Yasuaki INOUE
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