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IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
0.34 1.1
Volume E82-A No.11  (Publication Date:1999/11/25)
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Special Section on VLSI Design and CAD Algorithms

pp.2317-2317  FOREWORD
FOREWORD
Hiroto YASUURA  Mitsumasa KOYANAGI  
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pp.2318-2324  PAPER
Improving Dictionary-Based Code Compression in VLIW Architectures
Sang-Joon NAM  In-Cheol PARK  Chong-Min KYUNG  
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pp.2325-2337  PAPER
A Hardware/Software Cosynthesis System for Digital Signal Processor Cores
Nozomu TOGAWA  Masao YANAGISAWA  Tatsuo OHTSUKI  
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pp.2338-2346  PAPER
Hardware Synthesis from C Programs with Estimation of Bit Length of Variables
Osamu OGAWA  Kazuyoshi TAKAGI  Yasufumi ITOH  Shinji KIMURA  Katsumasa WATANABE  
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pp.2347-2355  PAPER
High-Level Synthesis with SDRAMs and RAMBUS DRAMs
Asheesh KHARE  Preeti R. PANDA  Nikil D. DUTT  Alexandru NICOLAU  
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pp.2356-2365  PAPER
A Performance Optimization Method for Pipelined ASIPs in Consideration of Clock Frequency
Katsuya SHINOHARA  Norimasa OHTSUKI  Yoshinori TAKEUCHI  Masaharu IMAI  
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pp.2366-2374  PAPER
A Memory Power Optimization Technique for Application Specific Embedded Systems
Tohru ISHIHARA  Hiroto YASUURA  
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pp.2375-2382  PAPER
Performance Evaluation of STRON: A Hardware Implementation of a Real-Time OS
Takumi NAKANO  Yoshiki KOMATSUDAIRA  Akichika SHIOMI  Masaharu IMAI  
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pp.2383-2389  PAPER
Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion
Tomoyuki YODA  Atsushi TAKAHASHI  
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pp.2390-2397  PAPER
Logic Minimization for Large-Scale Networks Based on Multi-Signal Implications
Masayuki YUGUCHI  Kazutoshi WAKABAYASHI  Takeshi YOSHIMURA  
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pp.2398-2406  PAPER
Representations of Multiple-Output Functions Using Binary Decision Diagrams for Characteristic Functions
Hafiz Md. HASAN BABU  Tsutomu SASAO  
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pp.2407-2413  PAPER
Exact Minimization of Free BDDs and Its Application to Pass-Transistor Logic Optimization
Kazuyoshi TAKAGI  Hiroshi HATAKEDA  Shinji KIMURA  Katsumasa WATANABE  
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pp.2414-2423  PAPER
Internet-Based Hierarchical Floorplan Design
Jiann-Horng LIN  Jing-Yang JOU  Iris Hui-Ru JIANG  
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pp.2424-2430  PAPER
An Algorithm to Position Fictitious Terminals on Borders of Divided Routing Areas
Atsushi KAMOSHIDA  Shuji TSUKIYAMA  
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pp.2431-2439  PAPER
Schedule-Clock-Tree Routing for Semi-Synchronous Circuits
Kazunori INOUE  Wataru TAKAHASHI  Atsushi TAKAHASHI  Yoji KAJITANI  
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pp.2440-2447  PAPER
Simplified Routing Procedure for a CAD-Verified FPGA
Takahiro MUROOKA  Atsushi TAKAHARA  Toshiaki MIYAZAKI  
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pp.2448-2454  PAPER
Efficient Forward Model Checking Algorithm for ω-Regular Properties
Hiroaki IWASHITA  Tsuneo NAKATA  
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pp.2455-2464  PAPER
A Partially Explicit Method for Efficient Symbolic Checking of Language Containment
Kiyoharu HAMAGUCHI  Michiyo ICHIHARA  Toshinobu KASHIWABARA  
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pp.2465-2474  PAPER
A Technique for Modelling Dynamic Reconfiguration with Improved Simulation Accuracy
Milan VASILKO  David CABANIS  
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pp.2475-2484  PAPER
Fast Instruction Cache Simulation for Hardware/Software Co-Design
Marcello LAJOLO  Luciano LAVAGNO  Alberto SANGIOVANNI-VINCENTELLI  
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pp.2485-2491  PAPER
A Proposition on Floating Gate Neuron MOS Macromodeling for Device Fabrications
Tadahiro OCHIAI  Hiroshi HATANO  
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pp.2492-2498  PAPER
RSPICE: A Fast and Robust Timing Simulator for Digital MOS VLSI
Xia CAI  Huazhong YANG  Yaowei JIA  Hui WANG  
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pp.2499-2504  PAPER
A VLSI Scan-Chain Optimization Algorithm for Multiple Scan-Paths
Susumu KOBAYASHI  Masato EDAHIRO  Mikio KUBO  
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pp.2505-2513  PAPER
Digital-Controlled Analog Circuits for Weighted-Sum Operations: Architecture, Implementation and Applications
Jie CHEN  Guoliang SHOU  Changming ZHOU  
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pp.2514-2520  PAPER
A High-Speed, Low-Power Phase Frequency Detector and Charge-Pump Circuits for High Frequency Phase-Locked Loops
Won-Hyo LEE  Sung-Dae LEE  Jun-Dong CHO  
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pp.2521-2526  PAPER
A New Single-Clock Flip-Flop for Half-Swing Clocking
Young-Su KWON  In-Cheol PARK  Chong-Min KYUNG  
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pp.2527-2529  LETTER
Parallel Test Structure in Latch Based Asynchronous Pipeline
Jing-ling YANG  Chiu-sing CHOY  Cheong-Fat CHAN  
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Special Section on Concurrent Systems Technology

pp.2531-2531  FOREWORD
FOREWORD
Masaru NANIWADA  
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pp.2532-2537  PAPER
A Method of Service Interference Detection with Rule-Based System and Extended Adjacency Matrix
Yoshio HARADA  
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pp.2538-2545  PAPER
Learning the Balance between Exploration and Exploitation via Reward
Tetsuya YOSHIDA  Koichi HORI  Shinichi NAKASUKA  
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pp.2546-2557  PAPER
A Compositional Approach for Constructing Communication Services and Protocols
Bhed Bahadur BISTA  Kaoru TAKAHASHI  Norio SHIRATORI  
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pp.2558-2565  PAPER
Time Complexity Analysis of the Minimal Siphon Extraction Problem of Petri Nets
Masahiro YAMAUCHI  Toshimasa WATANABE  
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pp.2566-2575  PAPER
Algorithms for Extracting Minimal Siphons Containing Specified Places in a General Petri Net
Masahiro YAMAUCHI  Toshimasa WATANABE  
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pp.2576-2578  LETTER
On Liveness of Extended Partially Ordered Condition Nets
Atsushi OHTA  Kohkichi TSUJI  Tomiji HISAMURA  
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pp.2579-2583  LETTER
A Two-Processor Scheduling Method for a Class of Program Nets with Unity Node Firing Time
Qi-Wei GE  
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Regular Section

pp.2584-2591  PAPER-Digital Signal Processing
A Novel CMA for the Hybrid of Adaptive Array and Equalizer in Mobile Communications
Maw-Lin LEOU  Hsueh-Jyh LI  
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pp.2592-2598  PAPER-Nonlinear Problems
Wave Propagation Phenomena of Phase States in Oscillators Coupled by Inductors as a Ladder
Masayuki YAMAUCHI  Masahiro WADA  Yoshifumi NISHIO  Akio USHIDA  
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pp.2599-2608  PAPER-VLSI Design Technology and CAD
A New Approach to the Ball Grid Array Package Routing
Shuenn-Shi CHEN  Jong-Jang CHEN  Trong-Yen LEE  Chia-Chun TSAI  Sao-Jie CHEN  
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pp.2609-2611  LETTER-Nonlinear Problems
IC Implementation of Current-Mode Chaotic Neuron Circuit
Nobuo KANOU  
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