IEICE Trans

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences

Volume E81-A No.12 (Publication Date:1998/12/25)

Special Section on VLSI Design and CAD Algorithms

pp.2475-2475 FOREWORD FOREWORD Masaharu IMAI Hitoshi KITAZAWA
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pp.2476-2484 PAPER-Layout Optimization A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout Tetsushi KOIDE Shin'ichi WAKABAYASHI
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pp.2485-2491 PAPER-Layout Optimization On Improved FPGA Greedy Routing Architectures Yu-Liang WU Douglas CHANG Malgorzata MAREK-SADOWSKA Shuji TSUKIYAMA
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pp.2492-2500 PAPER-Layout Optimization Layout Abstraction and Technology Retargeting for Leaf Cells Masahiro FUKUI Noriko SHINOMIYA Syunji SAIKA Toshiro AKINO Shigeo KUNINOBU
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pp.2501-2508 PAPER-Transistor-level Circuit Analysis, Design and Verification Efficient Curve Fitting Technique for Analysis of Interconnect Networks with Frequency-Dependent Parameters Yuichi TANJI Yoshifumi NISHIO Takashi SHIMAMOTO Akio USHIDA
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pp.2509-2514 PAPER-Transistor-level Circuit Analysis, Design and Verification Dual-Loop Digital PLL Design for Adaptive Clock Recovery Tae Hun KIM Beomsup KIM
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pp.2515-2520 PAPER-Timing Verification and Optimization Timing Verification of Sequential Logic Circuits Based on Controlled Multi-Clock Path Analysis Kazuhiro NAKAMURA Shinji KIMURA Kazuyoshi TAKAGI Katsumasa WATANABE
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pp.2521-2528 PAPER-Timing Verification and Optimization Design Optimization by Using Flexible Pipelined Modules Masahiro FUKUI Masakazu TANAKA Masaharu IMAI
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pp.2529-2537 PAPER-Logic Synthesis An Efficient Method for Finding an Optimal Bi-Decomposition Shigeru YAMASHITA Hiroshi SAWADA Akira NAGOYA
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pp.2538-2544 PAPER-Logic Synthesis Restructuring Logic Representations with Simple Disjunctive Decompositions Hiroshi SAWADA Shigeru YAMASHITA Akira NAGOYA
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pp.2545-2553 PAPER-Logic Synthesis Shared Multi-Terminal Binary Decision Diagrams for Multiple-Output Functions Hafiz Md. HASAN BABU Tsutomu SASAO
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pp.2554-2562 PAPER-Logic Synthesis Reduction of the Number of FPGA Blocks by Maximizing Flexibility of Internal Functions Takenori KOUDA Shigeru YAMASHITA Yahiko KAMBAYASHI
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pp.2563-2575 PAPER-High-level Synthesis A High-Level Synthesis System for Digital Signal Processing Based on Data-Flow Graph Enumeration Nozomu TOGAWA Takafumi HISAKI Masao YANAGISAWA Tatsuo OHTSUKI
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pp.2576-2584 PAPER-High-level Synthesis Module Selection Using Manufacturing Information Hiroyuki TOMIYAMA Hiroto YASUURA
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pp.2585-2594 PAPER-Design Reuse Program Slicing on VHDL Descriptions and Its Evaluation Shigeru ICHINOSE Mizuho IWAIHARA Hiroto YASUURA
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pp.2595-2604 PAPER-Co-design Language and Compiler for Optimizing Datapath Widths of Embedded Systems Akihiko INOUE Hiroyuki TOMIYAMA Takanori OKUMA Hiroyuki KANBARA Hiroto YASUURA
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pp.2605-2611 PAPER-Co-design Efficient and Flexible Cosimulation Environment for DSP Applications Wonyong SUNG Soonhoi HA
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pp.2612-2620 PAPER-Co-design An Optimization Algorithm for High Performance ASIP Design with Considering the RAM and ROM Sizes Nguyen Ngoc BINH Masaharu IMAI Yoshinori TAKEUCHI
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pp.2621-2629 PAPER-Compiler Instruction Scheduling to Reduce Switching Activity of Off-Chip Buses for Low-Power Systems with Caches Hiroyuki TOMIYAMA Tohru ISHIHARA Akihiko INOUE Hiroto YASUURA
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pp.2630-2639 PAPER-Compiler A Binding Algorithm for Retargetable Compilation to Non-orthogonal DSP Architectures Masayuki YAMAGUCHI Nagisa ISHIURA Takashi KAMBE
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pp.2640-2645 PAPER-Test A Test Methodology for Core-Based System LSIs Makoto SUGIHARA Hiroshi DATE Hiroto YASUURA
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pp.2646-2654 PAPER-Test Register-Transfer Level Testability Analysis and Its Application to Design for Testability Mizuki TAKAHASHI Ryoji SAKURAI Hiroaki NODA Takashi KAMBE
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pp.2655-2660 PAPER-LSI Architecture Evaluation of Shared DRAM for Parallel Processor System with Shared Memory Hiroyuki KURINO Keiichi HIRANO Taizo ONO Mitsumasa KOYANAGI
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pp.2661-2667 PAPER-LSI Architecture Effectiveness of a High Speed Context Switching Method Using Register Bank Jun-ichi ITO Takumi NAKANO Yoshinori TAKEUCHI Masaharu IMAI
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pp.2668-2672 PAPER-Digital Signal Processing Design and Analysis of Expanding Channels in Distributed Data Acquisition and Control System Xiubin ZHANG Yun HU Yinglu ZHANG
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pp.2673-2678 PAPER-VLSI Design Technology and CAD 200-ps Interchip-Delay Field-Programmable MCM for Telecommunications Masaru KATAYAMA Takahiro MUROOKA Toshiaki MIYAZAKI Kazuhiro SHIRAKAWA Kazuhiro HAYASHI Takaki ICHIMORI Kennosuke FUKAMI
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pp.2679-2687 PAPER-VLSI Design Technology and CAD A New Routing Method Considering Neighboring-Wire Capacitance Constraints Takumi WATANABE Kimihiro YAMAKOSHI Hitoshi KITAZAWA
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pp.2688-2693 PAPER-Algorithms and Data Structures New High-Order Associative Memory System Based on Newton's Forward Interpolation Hiromitsu HAMA Chunfeng XING Zhongkan LIU
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pp.2694-2702 PAPER-Graphs and Networks Reachability Problems of Random Digraphs Yushi UNO Toshihide IBARAKI
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pp.2703-2711 PAPER-Information Theory and Coding Theory A General Technique for Enumerative Encoding and Decoding Binary Runlength Sequences Volker BRAUN
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pp.2712-2714 LETTER-Numerical Analysis and Optimization Adaptive Accelerations of the Durand-Kerner Method Sachio KANNO
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pp.2715-2718 LETTER-Image Theory Monochromatic Visualization of Multimodal Images by Projection Pursuit Seiji HOTTA Kiichi URAHAMA
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