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IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
0.34 1.1
Volume E80-A No.2  (Publication Date:1997/02/25)
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Special Section on Analog Circuit Techniques for System-on-Chip Integration

pp.261-262  FOREWORD
FOREWORD
Atsushi IWATA  
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pp.263-275  INVITED PAPER
Approaches to Reducing Digital-Noise Coupling in CMOS Mixed-Signal LSIs
Toshiro TSUKADA  Keiko Makie-FUKUDA  
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pp.276-282  INVITED PAPER
Integration of a Power Supply for System-on-Chip
Satoshi MATSUMOTO  Masato MINO  Toshiaki YACHI  
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pp.283-290  PAPER
An Analog Two-Dimensional Discrete Cosine Transform Processor for Focal-Plane Image Compression
Shoji KAWAHITO  Makoto YOSHIDA  Yoshiaki TADOKORO  Akira MATSUZAWA  
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pp.291-295  PAPER
An Adder-Free Method for a Small Size π/4 Shift QPSK Signal Generator
Akira YASUDA  Hiroshi TANIMOTO  Chikau TAKAHASHI  Akira YAMAGUCHI  Masayuki KOIZUMI  
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pp.296-303  PAPER
A 156Mb/s CMOS Clock Recovery Circuit for Burst-Mode Transmission
Makoto NAKAMURA  Noboru ISHIHARA  Yukio AKAZAWA  
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pp.304-312  PAPER
Design of a Low-Voltage, Low-Power, High-Frequency CMOS Current-Mode VCO Circuit by Using 0.6µm MOS Devices
Yasuhiro SUGIMOTO  Takeshi UENO  Takaaki TSUJI  
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pp.313-320  PAPER
Substrate Noise Reduction Using Active Guard Band Filters in Mixed-Signal Integrated Circuits
Keiko Makie-FUKUDA  Satoshi MAEDA  Toshiro TSUKADA  Tatsuji MATSUURA  
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pp.321-327  PAPER
GaAs MESFET Linearized Transconductor and Active Load with no CMFB
Nobukazu TAKAI  Shigetaka TAKAGI  Nobuo FUJII  
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pp.328-333  PAPER
An 8-bit 200Ms/s 500mW BiCMOS ADC
Yoshio NISHIDA  Kazuya SONE  Kaori AMANO  Shoichi MATSUBA  Akira YUKAWA  
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pp.334-338  PAPER
A 350-MS/s 3.3V 8-bit CMOS D/A Converter Using a Delayed Driving Scheme
Hiroyuki KOHNO  Yasuyuki NAKAMURA  Takahiro MIKI  Hiroyuki AMISHIRO  Keisuke OKADA  Tadashi SUMI  
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pp.339-345  PAPER
A Built-In Self-Test for ADC and DAC in a Single-Chip Speech CODEC
Eiichi TERAOKA  Toru KENGAKU  Ikuo YASUI  Kazuyuki ISHIKAWA  Takahiro MATSUO  Hideyuki WAKADA  Narumi SAKASHITA  Yukihiko SHIMAZU  Takeshi TOKUDA  
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pp.346-348  LETTER
An Amplitude Limiting CDM by Using Majority Logic
Akihiko SUGIURA  Minoru INATSU  
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pp.349-352  LETTER
A 2.7-V Quasi-Microwave Si-Bipolar Quadrature Modulator without Tuning
Tsuneo TSUKAHARA  Tadao NAKAGAWA  Masahiro MURAGUCHI  
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pp.353-355  LETTER
An Offset-Compensated CMOS Programmable Gain Amplifier
Takafumi YAMAJI  Tetsuro ITAKURA  
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pp.356-359  LETTER
A Method to Improve CMRR for CMOS Operational Amplifier by Using Feedforward Technique
Eitake IBARAGI  Akira HYOGO  Keitaro SEKINE  
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pp.360-364  LETTER
A Current Mode Cyclic A/D Converter with Submicron Processes
Masaki KONDO  Hidetoshi ONODERA  Keikichi TAMARU  
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pp.365-376  PAPER-Digital Signal Processing
Multi-Band Decomposition of the Linear Prediction Error Applied to Adaptive AR Spectral Estimation
Fernando Gil V. RESENDE Jr.  Keiichi TOKUDA  Mineo KANEKO  Akinori NISHIHARA  
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pp.377-385  PAPER-Graphs and Networks
Score Sequence Problems of r-Tournaments
Masaya TAKAHASHI  
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pp.386-392  PAPER-Information Theory and Coding Theory
A Class of Trellis-Codes for Partial Response Channel
Tadashi WADAYAMA  Atsushi NAGAO  Koichiro WAKASUGI  Masao KASAHARA  
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pp.393-399  PAPER-Spread Spectrum Technologies and Applications
Performance Evaluation of a Variable Processing Gain DS/CDMA System
Dugin LYU  Yangsoo PARK  Iickho SONG  Hyung-Myung KIM  
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pp.400-406  PAPER-Concurrent Systems
Time-Action Alternating Model for Timed Processes and Its Symbolic Verification of Bisimulation Equivalence
Akio NAKATA  Teruo HIGASHINO  Kenichi TANIGUCHI  
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pp.407-412  PAPER-Neural Networks
Performance Evaluation of Two Algorithms for Learning in ANN Based on a Real Financial Prediction
Yadira SOLANO  Hiroaki IKEDA  
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pp.413-415  LETTER-Analog Signal Processing
A Realization of Active Current-Mode Resonator with Complex Coefficients Using CCIIs
Xiaoxing ZHANG  Noriyoshi KAMBAYASHI  Yuji SHINADA  
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pp.416-422  LETTER-Modeling and Simulation
Parallel Genetic Algorithm for Constrained Clustering
Myung-Mook HAN  Shoji TATSUMI  Yasuhiko KITAMURA  Takaaki OKUMOTO  
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pp.423-426  LETTER-Graphs and Networks
Modification of the Shufflenet Connectivity Graph for Balancing the Load in the Case of Uniform Traffic
Andrea BORELLA  Franco CHIARALUCE  
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pp.427-432  LETTER-Neural Networks
Analog CMOS Implementation of Approximate Identity Neural Networks
Massimo CONTI  
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