IEICE Trans

Online ISSN : 1745-1337

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences

Volume E95-A No.12 (Publication Date:2012/12/01)

Special Section on Information Theory and Its Applications

pp.2099-2099 FOREWORD FOREWORD Hiroshi KAMABE
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pp.2100-2106 PAPER-Source Coding On the Achievable Rate Region in the Optimistic Sense for Separate Coding of Two Correlated General Sources Hiroki KOGA
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pp.2107-2112 PAPER-Coding Theory Construction of Independent Set and Its Application for Designed Minimum Distance Junru ZHENG Takayasu KAIDA
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pp.2113-2121 PAPER-Coding Theory Analysis of Error Floors for Non-binary LDPC Codes over General Linear Group through q-Ary Memoryless Symmetric Channels Takayuki NOZAKI Kenta KASAI Kohichi SAKANIWA
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pp.2122-2129 PAPER-Coding Theory Simple Nonbinary Coding Strategy for Very Noisy Relay Channels Puripong SUTHISOPAPAN Kenta KASAI Anupap MEESOMBOON Virasit IMTAWIL Kohichi SAKANIWA
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pp.2130-2138 PAPER-Coding Theory The Expected Write Deficiency of Index-Less Indexed Flash Codes Yuichi KAJI
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pp.2139-2147 PAPER-Sequence Parameterization of Perfect Sequences over a Composition Algebra Takao MAEDA Takafumi HAYASHI
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pp.2148-2159 PAPER-Cryptography Cryptanalysis of Stream Ciphers from a New Aspect: How to Apply Key Collisions to Key Recovery Attack Jiageng CHEN Atsuko MIYAJI
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pp.2160-2167 PAPER-Spread Spectrum Two-Dimensional Optical CDMA Systems Based on MWOOC with Generalized Prime Sequences Agus SUSILO Tomoko K. MATSUSHIMA Yasuaki TERAMACHI
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pp.2168-2170 LETTER-Coding Theory Granular Gain of Low-Dimensional Lattices from Binary Linear Codes Misako KOTANI Shingo KAWAMOTO Motohiko ISAKA
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Special Section on VLSI Design and CAD Algorithms

pp.2171-2171 FOREWORD FOREWORD Masahiro NUMA
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pp.2172-2181 PAPER-Physical Level Design Yield-Driven Clock Skew Scheduling for Arbitrary Distributions of Critical Path Delays Yanling ZHI Wai-Shing LUK Yi WANG Changhao YAN Xuan ZENG
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pp.2182-2190 PAPER-Physical Level Design Via Programmable Structured ASIC Architecture “VPEX3” and CAD Design System Ryohei HORI Taisuke UEOKA Taku OTANI Masaya YOSHIKAWA Takeshi FUJINO
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pp.2191-2198 PAPER-Physical Level Design On Gate Level Power Optimization of Combinational Circuits Using Pseudo Power Gating Yu JIN Shinji KIMURA
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pp.2199-2207 PAPER-Physical Level Design Region Oriented Routing FPGA Architecture for Dynamic Power Gating Ce LI Yiping DONG Takahiro WATANABE
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pp.2208-2219 PAPER-Physical Level Design Novel Voltage Choice and Min-Cut Based Assignment for Dual-VDD System Haiqi WANG Sheqin DONG Tao LIN Song CHEN Satoshi GOTO
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pp.2220-2225 PAPER-Circuit Design Power Gating Implementation for Supply Noise Mitigation with Body-Tied Triple-Well Structure Yasumichi TAKAI Masanori HASHIMOTO Takao ONOYE
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pp.2226-2233 PAPER-Circuit Design A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells Shunsuke OKUMURA Shusuke YOSHIMOTO Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
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pp.2234-2241 PAPER-Circuit Design All-Digital Wireless Transceiver with Sub-Sampling Demodulation and Burst-Error Correction Sanad BUSHNAQ Makoto IKEDA Kunihiro ASADA
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pp.2242-2250 PAPER-Device and Circuit Modeling and Analysis A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits Junya KAWASHIMA Hiroshi TSUTSUI Hiroyuki OCHI Takashi SATO
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pp.2251-2260 PAPER-Device and Circuit Modeling and Analysis A Globally Convergent Nonlinear Homotopy Method for MOS Transistor Circuits Dan NIU Kazutoshi SAKO Guangming HU Yasuaki INOUE
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pp.2261-2271 PAPER-Device and Circuit Modeling and Analysis Power Distribution Network Optimization for Timing Improvement with Statistical Noise Model and Timing Analysis Takashi ENAMI Takashi SATO Masanori HASHIMOTO
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pp.2272-2283 PAPER-Device and Circuit Modeling and Analysis Bayesian Estimation of Multi-Trap RTN Parameters Using Markov Chain Monte Carlo Method Hiromitsu AWANO Hiroshi TSUTSUI Hiroyuki OCHI Takashi SATO
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pp.2284-2291 PAPER-Device and Circuit Modeling and Analysis Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits Kumpei YOSHIKAWA Yuta SASAKI Kouji ICHIKAWA Yoshiyuki SAITO Makoto NAGATA
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pp.2292-2300 PAPER-Logic Synthesis, Test and Verification A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning Shuta KIMURA Masanori HASHIMOTO Takao ONOYE
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pp.2301-2308 PAPER-Logic Synthesis, Test and Verification Evaluation of a New Power-Gating Scheme Utilizing Data Retentiveness on Caches Kyundong KIM Seidai TAKEDA Shinobu MIWA Hiroshi NAKAMURA
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pp.2309-2318 PAPER-Logic Synthesis, Test and Verification Transaction Ordering in Network-on-Chips for Post-Silicon Validation Amir Masoud GHAREHBAGHI Masahiro FUJITA
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pp.2319-2329 PAPER-Logic Synthesis, Test and Verification RazorProtector: Maintaining Razor DVS Efficiency in Large IR-Drop Zones by an Adaptive Redundant Data-Path Yukihiro SASAGAWA Jun YAO Takashi NAKADA Yasuhiko NAKASHIMA
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pp.2330-2337 PAPER-Logic Synthesis, Test and Verification A Formal Approach to Optimal Register Binding with Ordered Clocking for Clock-Skew Tolerant Datapaths Keisuke INOUE Mineo KANEKO
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pp.2338-2346 PAPER-High-Level Synthesis and System-Level Design Scan-Based Attack on AES through Round Registers and Its Countermeasure Youhua SHI Nozomu TOGAWA Masao YANAGISAWA
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pp.2347-2356 PAPER-High-Level Synthesis and System-Level Design Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration Yoshihiro ICHINOMIYA Tsuyoshi KIMURA Motoki AMAGASAKI Morihiro KUGA Masahiro IIDA Toshinori SUEYOSHI
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pp.2357-2363 PAPER-High-Level Synthesis and System-Level Design Achieving Maximum Performance for Bus-Invert Coding with Time-Splitting Transmitter Circuit Myungchul YOON
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pp.2364-2372 PAPER-High-Level Synthesis and System-Level Design FPGA Design of User Monitoring System for Display Power Control Tomoaki ANDO Vasily G. MOSHNYAGA Koji HASHIMOTO
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pp.2373-2383 PAPER-High-Level Synthesis and System-Level Design A High Level Design of Reconfigurable and High-Performance ASIP Engine for Image Signal Processing Hsuan-Chun LIAO Mochamad ASRI Tsuyoshi ISSHIKI Dongju LI Hiroaki KUNIEDA
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pp.2384-2391 PAPER-High-Level Synthesis and System-Level Design A 115 mW 1 Gbps Bit-Serial Layered LDPC Decoder for WiMAX Xiongxin ZHAO Xiao PENG Zhixiang CHEN Dajiang ZHOU Satoshi GOTO
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pp.2392-2395 LETTER-High-Level Synthesis and System-Level Design A Flexible Architecture for TURBO and LDPC Codes Yun CHEN Yuebin HUANG Chen CHEN Changsheng ZHOU Xiaoyang ZENG
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Regular Section

pp.2396-2406 PAPER-Digital Signal Processing Unified Constant Geometry Fault Tolerant DCT/IDCT for Image Codec System on a Display Panel Jaehee YOU
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pp.2407-2414 PAPER-Digital Signal Processing Low Complexity Systolic Array Structure for Extended QRD-RLS Equalizer Ji-Hye SHIN Young-Beom JANG
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pp.2415-2423 PAPER-Analog Signal Processing A Low-Cost Bit-Error-Rate BIST Circuit for High-Speed ADCs Based on Gray Coding Ya-Ting SHYU Ying-Zu LIN Rong-Sing CHU Guan-Ying HUANG Soon-Jyh CHANG
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pp.2424-2429 PAPER-VLSI Design Technology and CAD A High-Speed Low-Complexity Time-Multiplexing Reed-Solomon-Based FEC Architecture for Optical Communications Jeong-In PARK Hanho LEE
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pp.2430-2442 PAPER-VLSI Design Technology and CAD A Jitter Insertion and Accumulation Model for Clock Repeaters Monica FIGUEIREDO Rui L. AGUIAR
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pp.2443-2450 PAPER-VLSI Design Technology and CAD SSTA Scheme for Multiple Input Switching Case Based on Stochastic Collocation Method Gengsheng CHEN Chenxi QIAN Jun TAO
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pp.2451-2460 PAPER-Cryptography and Information Security Scalable Privacy-Preserving t-Repetition Protocol with Distributed Medical Data Ji Young CHUN Dowon HONG Dong Hoon LEE Ik Rae JEONG
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pp.2461-2469 PAPER-Communication Theory and Signals Performance Analysis of Hermite-Symmetric Subcarrier Coding for OFDM Systems over Fading Channels Fumihito SASAMORI Shiro HANDA
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pp.2470-2478 PAPER-Image Image Recovery by Decomposition with Component-Wise Regularization Shunsuke ONO Takamichi MIYATA Isao YAMADA Katsunori YAMAOKA
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pp.2479-2487 PAPER-General Fundamentals and Boundaries Statistical Learning Theory of Quasi-Regular Cases Koshi YAMADA Sumio WATANABE
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pp.2488-2492 LETTER-Cryptography and Information Security Anonymous Authentication Scheme without Verification Table for Wireless Environments Ryoichi ISAWA Masakatu MORII
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pp.2493-2497 LETTER-Information Theory Parametric Forms of the Achievable Rate Region for Source Coding with a Helper Tetsunao MATSUTA Tomohiko UYEMATSU Ryutaroh MATSUMOTO
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pp.2498-2501 LETTER-Image Robustness of Image Quality Factors for Environment Illumination Shogo MORI Gosuke OHASHI Yoshifumi SHIMODAIRA
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