IEICE Trans

Online ISSN : 1745-1337

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences

Volume E91-A No.12 (Publication Date:2008/12/01)

Special Section on VLSI Design and CAD Algorithms

pp.3413-3414 FOREWORD FOREWORD Nagisa ISHIURA
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pp.3415-3422 PAPER-Physical Level Design Highly Efficient Comparator Design Automation for TIQ Flash A/D Converter Insoo KIM Jincheol YOO JongSoo KIM Kyusun CHOI
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pp.3423-3430 PAPER-Physical Level Design A Power Grid Optimization Algorithm by Observing Timing Error Risk by IR Drop Yoshiyuki KAWAKAMI Makoto TERAO Masahiro FUKUI Shuji TSUKIYAMA
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pp.3431-3442 PAPER-Physical Level Design Efficient Hybrid Grid Synthesis Method Based on Genetic Algorithm for Power/Ground Network Optimization with Dynamic Signal Consideration Yun YANG Shinji KIMURA
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pp.3443-3450 PAPER-Physical Level Design Early Stage Power Supply Planning: A Heuristic Method for Codesign of Power/Ground Network and Floorplan Xiaoyi WANG Jin SHI Yici CAI Xianlong HONG
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pp.3451-3460 PAPER-Physical Level Design Character Projection Mask Set Optimization for Enhancing Throughput of MCC Projection Systems Makoto SUGIHARA Yusuke MATSUNAGA Kazuaki MURAKAMI
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pp.3461-3464 LETTER-Device and Circuit Modeling and Analysis Impact of Well Edge Proximity Effect on Timing Toshiki KANAMOTO Yasuhiro OGASAHARA Keiko NATSUME Kenji YAMAGUCHI Hiroyuki AMISHIRO Tetsuya WATANABE Masanori HASHIMOTO
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pp.3465-3473 PAPER-Device and Circuit Modeling and Analysis Adaptive Stochastic Collocation Method for Parameterized Statistical Timing Analysis with Quadratic Delay Model Yi WANG Xuan ZENG Jun TAO Hengliang ZHU Wei CAI
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pp.3474-3480 PAPER-Device and Circuit Modeling and Analysis Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration Masanori HASHIMOTO Jangsombatsiri SIRIPORN Akira TSUCHIYA Haikun ZHU Chung-Kuan CHENG
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pp.3481-3487 PAPER-Device and Circuit Modeling and Analysis Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution Shinya ABE Masanori HASHIMOTO Takao ONOYE
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pp.3488-3496 PAPER-Device and Circuit Modeling and Analysis New Gate Models for Gate-Level Delay Calculation under Crosstalk Effects Tae Il BAE Jin Wook KIM Young Hwan KIM
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pp.3497-3505 PAPER-Device and Circuit Modeling and Analysis Timing Criticality for Timing Yield Optimization Hyoun Soo PARK Wook KIM Dai Joon HYUN Young Hwan KIM
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pp.3506-3513 PAPER-Logic Synthesis, Test and Verification Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU
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pp.3514-3523 PAPER-Logic Synthesis, Test and Verification A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss Youhua SHI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
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pp.3524-3530 PAPER-Logic Synthesis, Test and Verification A Parallel Method to Extract Critical Areas of Net Pairs for Diagnosing Bridge Faults Keiichi SUEMITSU Toshiaki ITO Toshiki KANAMOTO Masayuki TERAI Satoshi KOTANI Shigeo SAWADA
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pp.3531-3538 PAPER-Logic Synthesis, Test and Verification Fine-Grained Power Gating Based on the Controlling Value of Logic Elements Lei CHEN Takashi HORIYAMA Yuichi NAKAMURA Shinji KIMURA
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pp.3539-3547 PAPER-Logic Synthesis, Test and Verification Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems Masato INAGI Yasuhiro TAKASHIMA Yuichi NAKAMURA Atsushi TAKAHASHI
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pp.3548-3555 PAPER-Logic Synthesis, Test and Verification Advanced Assertion-Based Design for Mixed-Signal Verification Alexander JESSER Stefan LAEMMERMANN Alexander PACHOLIK Roland WEISS Juergen RUF Lars HEDRICH Wolfgang FENGLER Thomas KROPF Wolfgang ROSENSTIEL
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pp.3556-3558 LETTER-High-Level Synthesis and System-Level Design High-Level Synthesis of Software Function Calls Masanari NISHIMURA Nagisa ISHIURA Yoshiyuki ISHIMORI Hiroyuki KANBARA Hiroyuki TOMIYAMA
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pp.3559-3567 PAPER-High-Level Synthesis and System-Level Design Formal Model for the Reduction of the Dynamic Energy Consumption in Multi-Layer Memory Subsystems Hongwei ZHU Ilie I. LUICAN Florin BALASA Dhiraj K. PRADHAN
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pp.3568-3575 PAPER-High-Level Synthesis and System-Level Design Optimal Common Sub-Expression Elimination Algorithm of Multiple Constant Multiplications with a Logic Depth Constraint Yuen-Hong Alvin HO Chi-Un LEI Hing-Kit KWAN Ngai WONG
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pp.3576-3584 PAPER-High-Level Synthesis and System-Level Design Way-Scaling to Reduce Power of Cache with Delay Variation Maziar GOUDARZI Tadayuki MATSUMURA Tohru ISHIHARA
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pp.3585-3595 PAPER-High-Level Synthesis and System-Level Design Simultaneous Optimization of Skew and Control Step Assignments in RT-Datapath Synthesis Takayuki OBATA Mineo KANEKO
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pp.3596-3606 PAPER-High-Level Synthesis and System-Level Design Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Michitaka KAMEYAMA
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pp.3607-3611 LETTER-Embedded, Real-Time and Reconfigurable Systems Efficient Encoding Architecture for IEEE 802.16e LDPC Codes Jeong Ki KIM Hyunseuk YOO Moon Ho LEE
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pp.3612-3621 PAPER-Embedded, Real-Time and Reconfigurable Systems Autonomous Repair Fault Tolerant Dynamic Reconfigurable Device Kentaro NAKAHARA Shin'ichi KOUYAMA Tomonori IZUMI Hiroyuki OCHI Yukihiro NAKAMURA
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pp.3622-3629 PAPER-Embedded, Real-Time and Reconfigurable Systems A High Performance Partially-Parallel Irregular LDPC Decoder Based on Sum-Delta Message Passing Schedule Wen JI Yuta ABE Takeshi IKENAGA Satoshi GOTO
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pp.3630-3637 PAPER-Embedded, Real-Time and Reconfigurable Systems High Throughput VLSI Architecture of a Fast Mode Decision Algorithm for H.264/AVC Intra Encoding Tianruo ZHANG Guifen TIAN Takeshi IKENAGA Satoshi GOTO
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pp.3638-3650 PAPER-Embedded, Real-Time and Reconfigurable Systems Wide-Range Motion Estimation Architecture with Dual Search Windows or High Resolution Video Coding Lan-Rong DUNG Meng-Chun LIN
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pp.3651-3662 PAPER-Embedded, Real-Time and Reconfigurable Systems Area-Efficient Reconfigurable Architecture for Media Processing Yukio MITSUYAMA Kazuma TAKAHASHI Rintaro IMAI Masanori HASHIMOTO Takao ONOYE Isao SHIRAKAWA
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Special Section on Signal Design and its Applications in Communications

pp.3663-3664 FOREWORD FOREWORD Pingzhi FAN Naoki SUEHIRO
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pp.3665-3678 INVITED PAPER On Almost Perfect Nonlinear Functions Claude CARLET
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pp.3679-3684 PAPER-Nonlinear Problems Autocorrelation of Some Quaternary Cyclotomic Sequences of Length 2p Young-Joon KIM Yun-Pyo HONG Hong-Yeop SONG
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pp.3685-3690 PAPER-Sequence Generalized M-Ary Related-Prime Sequences with Low Correlation Yun Kyoung HAN Kyeongcheol YANG
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pp.3691-3697 PAPER-Sequence New Families of Optimal Zero Correlation Zone Sequences Based on Interleaved Technique and Perfect Sequences Zhengchun ZHOU Zhen PAN Xiaohu TANG
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pp.3698-3702 PAPER-Sequence A New Construction Method of Zero-Correlation Zone Sequences Based on Complete Complementary Codes Chenggao HAN Takeshi HASHIMOTO Naoki SUEHIRO
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pp.3703-3711 PAPER-Sequence Construction and Performance Analysis of OVSF-ZCZ Codes Based on LS and GO Sequences Chao ZHANG Xiaoming TAO Jianhua LU
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pp.3712-3722 PAPER-Spread Spectrum Communications Adaptive CI-OSDM in Time-Frequency Selective Fading Channel Xiaoming TAO Chao ZHANG Jianhua LU Naoki SUEHIRO
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pp.3723-3730 PAPER-Spread Spectrum Communications Multitone-Hopping CDMA Using Feedback-Controlled Hopping Pattern for Decentralized Multiple Access Kazuki CHIBA Masanori HAMAMURA
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pp.3731-3737 PAPER-Coding Theory Some Upper Bounds on the Inverse Relative Dimension/Length Profile Peisheng WANG Yuan LUO A.J. Han VINCK
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pp.3738-3744 PAPER-Channel Equalization Design of a Fuzzy Based Outer Loop Controller for Improving the Training Performance of LMS Algorithm Ali OZEN Ismail KAYA Birol SOYSAL
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pp.3745-3748 LETTER-Sequence Zero Correlation Distribution of ZCZ Sequences Obtained from a Perfect Sequence and a Unitary Matrix Satoshi UEHARA Shuichi JONO Yasuyuki NOGAMI
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Regular Section

pp.3749-3756 PAPER-Systems and Control Motion Planning of Bimanual Robot Using Adaptive Model of Assembly Myun Joong HWANG Doo Yong LEE Seong Youb CHUNG
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pp.3757-3762 PAPER-Nonlinear Problems Fast Simulation Technique of Plane Circuits via Two-Layer CNN-Based Modeling Yuichi TANJI Hideki ASAI Masayoshi ODA Yoshifumi NISHIO Akio USHIDA
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pp.3763-3771 PAPER-Circuit Theory Broadband Equalizer Design with Commensurate Transmission Lines via Reflectance Modeling Metin ENGÜL Sddk B. YARMAN
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pp.3772-3782 PAPER-VLSI Design Technology and CAD A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits Koji OBATA Kazuyoshi TAKAGI Naofumi TAKAGI
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pp.3783-3792 PAPER-VLSI Design Technology and CAD Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation Model Yanming JIA Yici CAI Xianlong HONG
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pp.3793-3802 PAPER-VLSI Design Technology and CAD DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction Shigeru YAMASHITA Shin-ichi MINATO D. Michael MILLER
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pp.3803-3811 PAPER-VLSI Design Technology and CAD A Fast Clock Scheduling for Peak Power Reduction in LSI Yosuke TAKAHASHI Yukihide KOHIRA Atsushi TAKAHASHI
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pp.3812-3816 LETTER-Speech and Hearing Speech Enhancement Using Improved Adaptive Null-Forming in Frequency Domain with Postfilter Heng ZHANG Qiang FU Yonghong YAN
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pp.3817-3819 LETTER-Digital Signal Processing Rank M-Type L (RM L)-Filter for Image Denoising Francisco GALLEGOS-FUNES Jose VARELA-BENITEZ Volodymyr PONOMARYOV
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pp.3820-3823 LETTER-Digital Signal Processing Affine Projection Algorithm with Improved Data-Selective Method Using the Condition Number Sung Jun BAN Chang Woo LEE Sang Woo KIM
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pp.3824-3827 LETTER-Digital Signal Processing Constrained Total Least-Squares Algorithm for Hyperbolic Location Kai YANG Jianping AN Xiangyuan BU Zhan XU
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pp.3828-3832 LETTER-Cryptography and Information Security Anonymous Identity Based Encryption with Plaintext Awareness in the Two Identities Setting Changlu LIN Yong LI Qiupu ZHANG Dingfeng YE
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pp.3833-3836 LETTER-Cryptography and Information Security Identity-Based Authenticated Key Agreement Protocols without Bilinear Pairings Xuefei CAO Weidong KOU Yong YU Rong SUN
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pp.3837-3839 LETTER-Cryptography and Information Security Cryptanalysis and Enhancement of Modified Gateway-Oriented Password-Based Authenticated Key Exchange Protocol Kyung-Ah SHIM
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pp.3840-3842 LETTER-Communication Theory and Signals Low-Complexity Post-FFT Fine Frequency Synchronization for OFDM Young-Hwan YOU Sung-Jin KANG Hyoung-Kyu SONG
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pp.3843-3848 LETTER-Vision A Novel View of Color-Based Visual Tracker Using Principal Component Analysis Kiyoshi NISHIYAMA Xin LU
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pp.3849-3853 LETTER-Language, Thought, Knowledge and Intelligence Measures of End-User Information Competency in an Organizational Information Environment Chui Young YOON
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