IEICE Trans

Online ISSN : 1745-1337

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences

Volume E89-A No.12 (Publication Date:2006/12/01)

Special Section on VLSI Design and CAD Algorithms

pp.3377-3377 FOREWORD FOREWORD Hidetoshi ONODERA
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pp.3378-3386 PAPER-System Level Design Memory Size Computation for Real-Time Multimedia Applications Based on Polyhedral Decomposition Hongwei ZHU Ilie I. LUICAN Florin BALASA
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pp.3387-3396 PAPER-System Level Design Synchronization Verification in System-Level Design with ILP Solvers Thanyapat SAKUNKONCHAK Satoshi KOMATSU Masahiro FUJITA
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pp.3397-3407 PAPER-System Level Design The AMS Extension to System Level Design Language--SpecC Yu LIU Satoshi KOMATSU Masahiro FUJITA
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pp.3408-3415 PAPER-System Level Design Unified Representation for Speculative Scheduling: Generalized Condition Vector Kazutoshi WAKABAYASHI
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pp.3416-3426 PAPER-System Level Design An Efficient and Effective Algorithm for Online Task Placement with I/O Communications in Partially Reconfigurable FPGAs Mitsuru TOMONO Masaki NAKANISHI Shigeru YAMASHITA Kazuo NAKAJIMA Katsumasa WATANABE
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pp.3427-3434 PAPER-System Level Design Bit-Length Optimization Method for High-Level Synthesis Based on Non-linear Programming Technique Nobuhiro DOI Takashi HORIYAMA Masaki NAKANISHI Shinji KIMURA
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pp.3435-3442 PAPER-System Level Design Multi-Clock Cycle Paths and Clock Scheduling for Reducing the Area of Pipelined Circuits Bakhtiar Affendi ROSDI Atsushi TAKAHASHI
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pp.3443-3450 PAPER-Logic Synthesis Efficient Computation of Canonical Form under Variable Permutation and Negation for Boolean Matching in Large Libraries Debatosh DEBNATH Tsutomu SASAO
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pp.3451-3457 PAPER-Simulation and Verification Coverage Estimation Using Transition Perturbation for Symbolic Model Checking in Hardware Verification Xingwen XU Shinji KIMURA Kazunari HORIKAWA Takehiko TSUCHIYA
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pp.3458-3463 PAPER-Simulation and Verification Hierarchical-Analysis-Based Fast Chip-Scale Power Estimation Method for Large and Complex LSIs Yuichi NAKAMURA Takeshi YOSHIMURA
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pp.3464-3470 PAPER-Simulation and Verification Fast FPGA-Emulation-Based Simulation Environment for Custom Processors Yuichi NAKAMURA Kouhei HOSOKAWA
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pp.3471-3481 PAPER-Simulation and Verification A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA
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pp.3482-3490 PAPER-Simulation and Verification Delay Modeling and Critical-Path Delay Calculation for MTCMOS Circuits Naoaki OHKUBO Kimiyoshi USAMI
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pp.3491-3499 PAPER-Simulation and Verification On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature Takashi SATO Junji ICHIMIYA Nobuto ONO Masanori HASHIMOTO
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pp.3500-3509 PAPER-Circuit Synthesis Formal Design of Arithmetic Circuits Based on Arithmetic Description Language Naofumi HOMMA Yuki WATANABE Takafumi AOKI Tatsuo HIGUCHI
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pp.3510-3518 PAPER-Circuit Synthesis Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER
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pp.3519-3528 PAPER-Circuit Synthesis Design Method of High Performance and Low Power Functional Units Considering Delay Variations Kouichi WATANABE Masashi IMAI Masaaki KONDO Hiroshi NAKAMURA Takashi NANYA
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pp.3529-3537 PAPER-Circuit Synthesis A Structural Approach for Transistor Circuit Synthesis Hiroaki YOSHIDA Makoto IKEDA Kunihiro ASADA
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pp.3538-3545 PAPER-Circuit Synthesis A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays Shingo TAKAHASHI Shuji TSUKIYAMA Masanori HASHIMOTO Isao SHIRAKAWA
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pp.3546-3550 PAPER-Physical Design LSI Design Flow for Shot Reduction of Character Projection Electron Beam Direct Writing Using Combined Cell Stencil Taisuke KAZAMA Makoto IKEDA Kunihiro ASADA
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pp.3551-3559 PAPER-Physical Design Routing of Monotonic Parallel and Orthogonal Netlists for Single-Layer Ball Grid Array Packages Yoichi TOMIOKA Atsushi TAKAHASHI
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pp.3560-3568 PAPER-Interconnect Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design Toshiki KANAMOTO Tatsuhiko IKEDA Akira TSUCHIYA Hidetoshi ONODERA Masanori HASHIMOTO
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pp.3569-3578 PAPER-Interconnect Simple Waveform Model of Inductive Interconnects by Delayed Quadratic Transfer Function with Application to Scaling Trend of Inductive Effects in VLSI's Danardono Dwi ANTONO Kenichi INAGAKI Hiroshi KAWAGUCHI Takayasu SAKURAI
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pp.3579-3584 PAPER-Interconnect Statistical Modeling of a Via Distribution for Yield Estimation Takumi UEZONO Kenichi OKADA Kazuya MASU
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pp.3585-3593 PAPER-Interconnect Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line Akira TSUCHIYA Masanori HASHIMOTO Hidetoshi ONODERA
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pp.3594-3601 PAPER-VLSI Architecture A VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization Yang SONG Zhenyu LIU Takeshi IKENAGA Satoshi GOTO
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pp.3602-3612 PAPER-VLSI Architecture Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule Kazunori SHIMIZU Tatsuyuki ISHIKAWA Nozomu TOGAWA Takeshi IKENAGA Satoshi GOTO
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pp.3613-3622 PAPER-VLSI Architecture VLSI Implementation of a Modified Efficient SPIHT Encoder Win-Bin HUANG Alvin W. Y. SU Yau-Hwang KUO
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pp.3623-3633 PAPER-VLSI Architecture A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture Junichi MIYAKOSHI Yuichiro MURACHI Tetsuro MATSUNO Masaki HAMAMOTO Takahiro IINUMA Tomokazu ISHIHARA Hiroshi KAWAGUCHI Masayuki MIYAMA Masahiko YOSHIMOTO
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pp.3634-3641 PAPER-VLSI Architecture A 0.3-V Operating, V_th-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond Yasuhiro MORITA Hidehiro FUJIWARA Hiroki NOGUCHI Kentaro KAWAKAMI Junichi MIYAKOSHI Shinji MIKAMI Koji NII Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
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pp.3642-3651 PAPER-VLSI Architecture A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline Kentaro KAWAKAMI Jun TAKEMURA Mitsuhiko KURODA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
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pp.3652-3658 PAPER-VLSI Architecture Fault Tolerant Dynamic Reconfigurable Device Based on EDAC with Rollback Kentaro NAKAHARA Shin'ichi KOUYAMA Tomonori IZUMI Hiroyuki OCHI Yukihiro NAKAMURA
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pp.3659-3665 PAPER-VLSI Architecture A Parallel-In Folding Technique for High-Order FIR Filter Implementation Lan-Rong DUNG Hsueh-Chih YANG
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pp.3666-3670 LETTER-Interconnect Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation Toshiki KANAMOTO Shigekiyo AKUTSU Tamiyo NAKABAYASHI Takahiro ICHINOMIYA Koutaro HACHIYA Atsushi KUROKAWA Hiroshi ISHIKAWA Sakae MUROMOTO Hiroyuki KOBAYASHI Masanori HASHIMOTO
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Regular Section

pp.3671-3677 PAPER-Engineering Acoustics Target-Oriented Acoustic Radiation Generation Technique for Sound Field Control Yuan WEN Jun YANG Woon-Seng GAN
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pp.3678-3684 PAPER-Digital Signal Processing Estimation of Color Images by Box Splines from Their Observation through Honeycomb Color Filter Tomoko YOKOKAWA Masaru KAMADA Yasuhiro OHTAKI Tatsuhiro YONEKURA
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pp.3685-3692 PAPER-Analog Signal Processing Miller Capacitor with Wide Input Range and Its Application to PLL Loop Filter Masahiro YOSHIOKA Nobuo FUJII
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pp.3693-3698 PAPER-Nonlinear Problems Necessary and Sufficient Conditions for One-Dimensional Discrete-Time Autonomous Binary Cellular Neural Networks to Be Stable Tetsuo NISHI Norikazu TAKAHASHI Hajime HARA
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pp.3699-3709 PAPER-Algorithms and Data Structures On the Expected Prediction Error of Orthogonal Regression with Variable Components Katsuyuki HAGIWARA Hiroshi ISHITANI
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pp.3710-3723 PAPER-Information Theory Properties of a Word-Valued Source with a Non-prefix-free Word Set Takashi ISHIDA Masayuki GOTO Toshiyasu MATSUSHIMA Shigeichi HIRASAWA
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pp.3724-3729 LETTER-Digital Signal Processing Steady-State Properties of a CORDIC-Based Adaptive ARMA Lattice Filter Shin'ichi SHIRAISHI Miki HASEYAMA Hideo KITAJIMA
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pp.3730-3731 LETTER-Circuit Theory Grounded-Capacitor First-Order Filter Using Minimum Components Hua-Pin CHEN Kuo-Hsiung WU
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pp.3732-3735 LETTER-Information Security New Digital Fingerprint Code Construction Scheme Using Group-Divisible Design InKoo KANG Kishore SINHA Heung-Kyu LEE
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pp.3736-3738 LETTER-Concurrent Systems First Derivatives Estimation of Nonlinear Parameters in Hybrid System Jung-Wook PARK Byoung-Kon CHOI Kyung-Bin SONG
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