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IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Volume E82-A No.2  (Publication Date:1999/02/25)
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Special Section on VLSI for Digital Signal Processing

pp.183-183  FOREWORD
FOREWORD
Hitoshi KIYA  
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pp.184-196  INVITED PAPER
Low-Power Architectures for Programmable Multimedia Processors
Takao NISHITANI  
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pp.197-205  INVITED PAPER
System Electronics Technologies for Video Processing and Applications
Tomio KISHIMOTO  Hironori YAMAUCHI  Ryota KASAI  
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pp.206-214  PAPER
Media Core Processor for Multimedia Application System
Kosuke YOSHIOKA  Makoto HIRAI  Kozo KIMURA  Tokuzo KIYOHARA  
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pp.215-222  PAPER
A Real-Time Low-Rate Video Compression Algorithm Using Multi-Stage Hierarchical Vector Quantization
Kazutoshi KOBAYASHI  Kazuhiko TERADA  Hidetoshi ONODERA  Keikichi TAMARU  
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pp.223-229  PAPER
A Pipelined Architecture for Normalized LMS Adaptive Digital Filters
Akio HARADA  Kiyoshi NISHIKAWA  Hitoshi KIYA  
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pp.230-237  PAPER
A Transformation Method of a CORDIC ARMA Lattice Filter for Signal Synthesis
Shin'ichi SHIRAISHI  Miki HASEYAMA  Hideo KITAJIMA  
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pp.238-245  PAPER
Performance Enhancement on Digital Signal Processors with Complex Arithmetic Capability
Yoshimasa NEGISHI  Eiji WATANABE  Akinori NISHIHARA  Takeshi YANAGISAWA  
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pp.246-254  PAPER
A Method for Circular Pattern Recognition in a Binary Image and Its Implementation onto an FPGA
Yusuke TOKUNAGA  Takahiro INOUE  
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Special Section on Analog Circuit Techniques and Related Topics

pp.255-255  FOREWORD
FOREWORD
Hiroshi TANIMOTO  
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pp.256-270  INVITED PAPER
Design of Fully Balanced Analog Systems Based on Ordinary and/or Modified Single-Ended Opamps
Zdzis taw CZARNUL  Tetsuro ITAKURA  Noriaki DOBASHI  Takashi UENO  Tetsuya IIDA  Hiroshi TANIMOTO  
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pp.271-278  INVITED PAPER
Substrate Noise Simulation Techniques for Analog-Digital Mixed LSI Design
Makoto NAGATA  Atsushi IWATA  
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pp.279-285  PAPER
A 10 Bit Current-Mode CMOS A/D Converter with a Current Predictor and a Modular Current Reference
Soung Hoon SHIM  Kwang Sub YOON  
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pp.286-292  PAPER
A 1.5 V, 8 mW, 8 b, 15 Msps BiCMOS A/D Converter
Michio YOTSUYANAGI  Hiroshi HASEGAWA  Masaharu SATO  
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pp.293-300  PAPER
Low-Power Area-Efficient Pipelined A/D Converter Design Using a Single-Ended Amplifier
Daisuke MIYAZAKI  Shoji KAWAHITO  Yoshiaki TADOKORO  
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pp.301-306  PAPER
Differential Analog Data Path DC Offset Calibration Methods
Takeo YASUDA  Hajime ANDOH  
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pp.307-312  PAPER
A CMOS Offset Phase Locked Loop for a GSM Transmitter
Taizo YAMAWAKI  Masaru KOKUBO  Hiroshi HAGISAWA  
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pp.313-319  PAPER
A 1.9-GHz Direct Conversion Transmitter IC with Low Power On-Chip Frequency Doubler
Shoji OTAKA  Ryuichi FUJIMOTO  Hiroshi TANIMOTO  
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pp.320-326  PAPER
GaAs FET Current-Mode Integrators and Their Application to Filters
Nobukazu TAKAI  Nobuo FUJII  
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pp.327-334  PAPER
A CMOS Analog Multiplier Free from Mobility Reduction and Body Effect
Eitake IBARAGI  Akira HYOGO  Keitaro SEKINE  
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pp.335-340  PAPER
Multi-Input Floating Gate Differential Amplifier and Applications to Intelligent Sensors
Takeyasu SAKAI  Hiromasa NAGAI  Takashi MATSUMOTO  
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pp.341-347  PAPER
A Fast and Accurate Method of Redesigning Analog Subcircuits for Technology Scaling
Seiji FUNABA  Akihiro KITAGAWA  Toshiro TSUKADA  Goichi YOKOMIZO  
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pp.348-355  PAPER
Layout Dependent Matching Analysis of CMOS Circuits
Kenichi OKADA  Hidetoshi ONODERA  Keikichi TAMARU  
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pp.356-363  PAPER
An Analog-Digital Merged Neural Circuit Using Pulse Width Modulation Technique
Takashi MORIE  Jun FUNAKOSHI  Makoto NAGATA  Atsushi IWATA  
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pp.364-369  PAPER
Integrated Circuits of Map Chaos Generators
Hidetoshi TANAKA  Shigeo SATO  Koji NAKAJIMA  
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pp.370-377  PAPER
A Content-Addressable Memory Using "Switched Diffusion Analog Memory with Feedback Circuit"
Tomochika HARADA  Shigeo SATO  Koji NAKAJIMA  
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pp.378-379  LETTER
Low Voltage High-Speed CMOS Square-Law Composite Transistor Cell
Changku HWANG  Akira HYOGO  Hong-sun KIM  Mohammed ISMAIL  Keitaro SEKINE  
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Regular Section

pp.380-389  PAPER-Systems and Control
A Simple Pole-Assignment Scheme for Designing Multivariable Self-Tuning Controllers
Toru YAMAMOTO  Yujiro INOUYE  Masahiro KANEDA  
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pp.390-393  PAPER-Information Security
Construct Message Authentication Code with One-Way Hash Functions and Block Ciphers
Yi-Shiung YEH  Chan-Chi WANG  
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pp.394-397  LETTER-Graphs and Networks
The Complexity of an Optimal File Transfer Problem
Yoshihiro KANEKO  Shoji SHINODA  
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pp.398-402  LETTER-Neural Networks
Adaptive Simulated Annealing in CNN Template Learning
Brett CHANDLER  Csaba REKECZKY  Yoshifumi NISHIO  Akio USHIDA  
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pp.403-406  LETTER-Image Theory
Two-Level Quantizer Design Using Genetic Algorithm
Wen-Jan CHEN  Shen-Chuan TAI  Po-Jen CHENG  
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