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IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Volume E76-A No.10  (Publication Date:1993/10/25)
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Special Section on Nets-Oriented Software Specification and Design

pp.1565-1566  FOREWORD
FOREWORD
Shinichi HONIDEN  
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pp.1567-1579  INVITED PAPER
PDM: Petri Net Based Development Methodology for Distributed Systems
Mikio AOYAMA  
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pp.1580-1590  PAPER
Algebraic Approaches for Nets Using Formulas to Describe Practical Software Systems
kazuhito OHMAKI  Yutaka SATO  Ichiro OGATA  Kokichi FUTATSUGI  
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pp.1591-1597  PAPER
State Diagram Matrix for Hierarchical Specification of Reactive System
Tomohiro MURATA  Kenzou KURIHARA  Ayako ASHIDA  
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pp.1598-1606  PAPER
Application of Petri Nets to Sequence Control
Yoichi NAGAO  Hironobu URABE  Shinichi NAKANO  Sadatoshi KUMAGAI  
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pp.1607-1609  LETTER
On a Sufficient Condition for a Matrix to be the Synchronic Distance Matrix of a Marked Graph
Kiyoshi MIKAMI  Hiroshi TAMURA  Masakazu SENGOKU  Yoshio YAMAGUCHI  
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pp.1610-1614  LETTER
A Study on the Design and Reliability Analysis of Concurrent System by Petri Nets: A Case on Lift System
Gy Bum KIM  Gang Soo LEE  Jung Mo YOON  
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Special Section on VLSI Design and CAD Algorithms

pp.1615-1616  FOREWORD
FOREWORD
Winfried HAHN  Takeshi YOSHIMURA  
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pp.1617-1625  PAPER
High-Level Synthesis Using Given Datapath Information
Toshiaki MIYAZAKI  Mitsuo IKEDA  
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pp.1626-1635  PAPER
The lmprovement in Performance-Driven Analog LSI Layout System LIBRA
Tomohiko OHTSUKA  Nobuyuki KUROSAWA  Hiroaki KUNIEDA  
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pp.1636-1644  PAPER
An Optimal Channel Pin Assignment Algorithm for Hierarchical Building-Block Layout Design
Tetsushi KOIDE  Shin'ichi WAKABAYASHI  Noriyoshi YOSHIDA  
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pp.1645-1651  PAPER
An Efficient Algorithm for Multiple Folded Gate Matrix Layout
Shoichiro YAMADA  Shunichi NAKAYAMA  
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pp.1652-1658  PAPER
MINT--An Exact Algorithm for Finding Minimum Test Set--
Yusuke MATSUNAGA  
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pp.1659-1665  PAPER
Hierarchical Analysis System for VLSI Power Supply Network
Takeshi YOSHITOME  
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pp.1666-1675  PAPER
A Proposal of High Speed and Low Power Data Transmission Method for VLSIs by Reduced-Swing Signal
Makoto IKEDA  Kunihiro ASADA  
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pp.1676-1683  PAPER
Compact Test Sequences for Scan-Based Sequential Circuits
Hiroyuki HIGUCHI  Kiyoharu HAMAGUCHI  Shuzo YAJIMA  
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pp.1684-1693  PAPER
A Hardware Accelerator for Design-Rule Checking in a Bit-Mapping CAD System
Cong-Kha PHAM  Katsufusa SHONO  
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pp.1694-1704  PAPER
A Hierarchical Global Router for Mscro-Block-Embedded Sea-of-Gates
Mototaka KURIBAYASHI  Masaaki YAMADA  Takashi MITSUHASHI  Nobuyuki GOTO  
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pp.1705-1712  PAPER
Reconfigurable Machine and its Application to Logic Simulation
Nasahiro TOMITA  Naoaki SUGANUMA  Kotaro HIRANO  
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pp.1713-1720  PAPER
An ASIP Instruction Set Optimization Algorithm with Functional Module Sharing Constraint
Alauddin Y. ALOMARY  Masaharu IMAI  Nobuyuki HIKICHI  
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pp.1721-1729  PAPER
BEM-: An Arithmetic Boolean Expression Manipulator Using BDDs
Shin-ichi MINATO  
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pp.1730-1737  PAPER
Test Sequence Generation for Sequential Circuits with Distinguishing Sequences
Yoshinobu HIGAMI  Seiji KAJIHARA  Kozo KINOSHITA  
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pp.1738-1745  PAPER
Restrictive Channel Routing with Evolution Programs
Xingzhao LIU  Akio SAKAMOTO  Takashi SHIMAMOTO  
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pp.1746-1754  PAPER
A Global Routing Algorithm Based on the Multi-Commodity Network Flow Method
Yoichi SHIRAISHI  Jun'ya SAKEMI  Kazuyuki FUKUDA  
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pp.1755-1759  PAPER
Prciseness of Discrete Time Verification
Shinji KIMURA  Shunsuke TSUBOTA  Hiromasa HANEDA  
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pp.1760-1769  PAPER
COACH:A Computer Aided Design Tool for Computer Architects
Hiroki AKABOSHI  Hiroto YASUURA  
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pp.1770-1774  LETTER
Test Generation for Sequential Circits Using Partitioned Image Computation
Hoyong CHOI  Hironori MAEDA  Takashi KOHARA  Nagisa ISHIURA  Isao SHIRAKAWA  Akira MOTOHARA  
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Regular Section

pp.1775-1780  PAPER-Digital Signal Processing
Interval Properties of Lattice Allpass Fiters with Applications
Saed SAMADI  Akinori NISHIHARA  Nobuo FUJII  
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pp.1781-1789  PAPER-Queueing Theory
Consecutive Customer Loss Phenomenon due to Buffer Overflow in Finite Buffer Queueing System
Masaharu KOMATSU  Kozo KINOSHITA  
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pp.1790-1803  PAPER-Information Theory and Coding Theory
A Compostite Signal Detection Scheme in Additive and Signal-Dependent Noise
Sangyoub KIM  Iickho SONG  Sun Yong KIM  
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pp.1804-1811  PAPER-Neural Networks
Exploiting Parallelism in Neural Networks on a Dynamic Data-Driven System
Ali M. ALHAJ  Hiroaki TERADA  
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pp.1812-1821  PAPER-Nonlinear Circuits and Systems
A Simple Algorithm for Finding All Solutions of Piecewise-Linear Resistive Circuits
Kiyotaka YAMAMURA  
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pp.1822-1829  PAPER-Numerical Analysis and Self-Validation
A Parallel Scheduling of Multi-Step Diakoptics for Three Dimensional Finite Differece Method
Kazuhiro MOTEGI  Shigeyoshi WATANABE  
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pp.1830-1848  PAPER-Parallel/Multidimensional Signal Processing
The Optimum Approximation of Muliti-Dimensional Signals Using Parallel Wavelet Filter Banks
Takuro KIDA  
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pp.1849-1857  PAPER-VLSI Design Technology
An Integer Programming Approach to Instruction Set Selection Problem
Alauddin Y. ALOMARY  Masaharu IMAI  Jun SATO  Nobuyuki HIKICHI  
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pp.1858-1860  LETTER-Acoustics
A Proposal of a Recognition System for the Specices of Birds Receiving Birdcalls--An Application of Recognition Systems for Environmental Sound--
Takehiko ASHIYA  Masao NAKAGAWA  
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pp.1861-1862  LETTER-Acoustics
A Noncontact Thickness Measurement of Thin Samples Using 40 kHz Ultrasonic Wave
Kazuhiko IMANO  Daitaro OKUYAMA  Noriyoshi CHUBACHI  
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pp.1863-1865  LETTER-Analog Circuits and Signal Processing
A Third-Order Low-Pass Notch RC Active Filter with a Minimum Number of Equal-Valued Capacitors
Yukio ISHIBASHI  
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pp.1866-1869  LETTER-Control and Computing
A New Design Method for Nonminimum Phase Adaptive Control System with Disturbances Based on Pole-Zero Placement
Takashi YAHAGI  Jianming LU  
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pp.1870-1873  LETTER-Digital Image Processing
Generating Binary Random Images by a Discrete-Valued Auto-Regressive Equation
Junichi NAKAYAMA  
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pp.1874-1876  LETTER-Information Theory and Coding Theory
A Derivation of the Phase Difference between n-Tuples of an M-Sequence by Arithmetic a Finite Field
Tsutomu MORIUCHI  Kyoki IMAMURA  
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pp.1877-1883  LETTER-Neural Networks
Generalization Ability of Extended Cascaded Artificial Neural Network Architecture
Joarder KAMRUZZAMAN  Yukio KUMAGAI  Hiromitsu HIKITA  
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