IEICE Trans

Zule XU

Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector Zule XU Anugerah FIRDAUZI Masaya MIYAHARA Kenichi OKADA Akira MATSUZAWA
Publication: Publication Date: 2019/07/01 Vol. E102-C No. 7 pp. 520-529 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies) Category: Keyword: type-I, digital phase-locked loop, ring-based PLL,
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Robustness Evaluation of Restricted Boltzmann Machine against Memory and Logic Error Yasushi FUKUDA Zule XU Takayuki KAWAHARA
Publication: Publication Date: 2017/12/01 Vol. E100-C No. 12 pp. 1118-1121 Type of Manuscript: BRIEF PAPER Category: Integrated Electronics Keyword: IoT, neural network, RBM, DBN, soft error,
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Physical-Weight-Based Measurement Methodology Suppressing Noise or Reducing Test Time for High-Resolution Low-Speed ADCs Mitsutoshi SUGAWARA Zule XU Akira MATSUZAWA
Publication: Publication Date: 2017/06/01 Vol. E100-C No. 6 pp. 576-583 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies) Category: Keyword: AD converter, DA converter, measurement, slow-ramp, histogram method, moment method, missing code,
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High Resolution Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Compensated Charge-Pump Integrator Anugerah FIRDAUZI Zule XU Masaya MIYAHARA Akira MATSUZAWA
Publication: Publication Date: 2017/06/01 Vol. E100-C No. 6 pp. 548-559 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies) Category: Keyword: charge-pump, delta-sigma, SAR ADC, time-to-digital converter,
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A Saturating-Integrator-Based Behavioral Model of Ring Oscillator Facilitating PLL Design Zule XU Takayuki KAWAHARA
Publication: Publication Date: 2017/04/01 Vol. E100-C No. 4 pp. 370-372 Type of Manuscript: BRIEF PAPER Category: Keyword: ring oscillator, phase-locked loop, behavioral model, digital PLL,
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Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell Mitsutoshi SUGAWARA Kenji MORI Zule XU Masaya MIYAHARA Kenichi OKADA Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/12/01 Vol. E99-A No. 12 pp. 2435-2443 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: analog synthesis, RDAC, slice-based layout, SKILL language,
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Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC Zule XU Seungjong LEE Masaya MIYAHARA Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/02/01 Vol. E98-A No. 2 pp. 476-484 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: ADPLL, charge pump, SAR-ADC, sub-picosecond resolution, TDC, time-to-charge conversion,
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Loop Design Optimization of Fourth-Order Fractional-N PLL Frequency Synthesizers Jun Gyu LEE Zule XU Shoichi MASUI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/08/01 Vol. E95-A No. 8 pp. 1337-1346 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: phase-locked loop, frequency synthesizer, loop design, settling time, process variations,
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Self-Dithered Digital Delta-Sigma Modulators for Fractional-N PLL Zule XU Jun Gyu LEE Shoichi MASUI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/06/01 Vol. E94-C No. 6 pp. 1065-1068 Type of Manuscript: BRIEF PAPER Category: Keyword: digital delta-sigma modulator (DDSM), fractional-N PLL, dither,
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