Zhangcai HUANG


An Effective Model of the Overshooting Effect for Multiple-Input Gates in Nanometer Technologies
Li DING Zhangcai HUANG Atsushi KUROKAWA Jing WANG Yasuaki INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/05/01
Vol. E97-A  No. 5  pp. 1059-1074
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
gate delayovershooting effectmultiple-input gatesnanometer technology
 Summary | Full Text:PDF

A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect
Minglu JIANG Zhangcai HUANG Atsushi KUROKAWA Qiang LI Bin LIN Yasuaki INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/05/01
Vol. E94-A  No. 5  pp. 1201-1209
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
static timing analysisgate delayeffective capacitancenon-iterative
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Memristor Model for SPICE
Xuliang ZHANG Zhangcai HUANG Juebang YU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3  pp. 355-360
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
memristorSPICE modelChua's circuitmemristor device and circuit simulation
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Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model
Minglu JIANG Zhangcai HUANG Atsushi KUROKAWA Shuai FANG Yasuaki INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/10/01
Vol. E92-A  No. 10  pp. 2531-2539
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
Category: Nonlinear Problems
Keyword: 
static timing analysisgate delayeffective capacitanceThevenin model
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A Highly Linear and Wide Input Range Four-Quadrant CMOS Analog Multiplier Using Active Feedback
Zhangcai HUANG Minglu JIANG Yasuaki INOUE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/06/01
Vol. E92-C  No. 6  pp. 806-814
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
analog multiplieranalog signal processingactive feedback
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An Effective SPICE3 Implementation of the Compound Element Pseudo-Transient Algorithm
Hong YU Yasuaki INOUE Kazutoshi SAKO Xiaochuan HU Zhangcai HUANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/10/01
Vol. E90-A  No. 10  pp. 2124-2131
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
Category: Nonlinear Circuits
Keyword: 
pseudo-transient analysiscompound elementDC operating pointSPICE3 implementationJacobian matrix
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Behavioral Circuit Macromodeling and Analog LSI Implementation for Automobile Engine Intake System
Zhangcai HUANG Yasuaki INOUE Hong YU Jun PAN Yun YANG Quan ZHANG Shuai FANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/04/01
Vol. E90-A  No. 4  pp. 732-740
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
automobile engine intake systemanalog LSI implementationbehavioral circuit macromodeling
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A Low-Power Sub-1-V Low-Voltage Reference Using Body Effect
Jun PAN Yasuaki INOUE Zheng LIANG Zhangcai HUANG Weilun HUANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/04/01
Vol. E90-A  No. 4  pp. 748-755
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
low-powerlow-voltageCMOSreferencebody effecttemperature coefficientback-gate
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An Effective Pseudo-Transient Algorithm for Finding DC Solutions of Nonlinear Circuits
Hong YU Yasuaki INOUE Yuki MATSUYA Zhangcai HUANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/10/01
Vol. E89-A  No. 10  pp. 2724-2731
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
Category: Modelling, Systems and Simulation
Keyword: 
pseudo-transient analysisDC operating-pointnonlinear circuitcompound pseudo-element
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Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills
Atsushi KUROKAWA Akira KASEBE Toshiki KANAMOTO Yun YANG Zhangcai HUANG Yasuaki INOUE Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/04/01
Vol. E89-A  No. 4  pp. 847-855
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
dummy fillcapacitance extractioncapacitance formulainterconnect
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Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay
Zhangcai HUANG Atsushi KUROKAWA Yun YANG Hong YU Yasuaki INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/04/01
Vol. E89-A  No. 4  pp. 840-846
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
CMOS inverterovershooting effectdeep submicrontiming analysis
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Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays
Atsushi KUROKAWA Hiroo MASUDA Junko FUJII Toshinori INOSHITA Akira KASEBE Zhangcai HUANG Yasuaki INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/04/01
Vol. E89-A  No. 4  pp. 856-864
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
interconnectworst-case delaystatic timing analysisprocess variationcapacitance extraction
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Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew
Zhangcai HUANG Atsushi KUROKAWA Jun PAN Yasuaki INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3367-3374
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Prediction and Analysis
Keyword: 
static timing analysisgate slewCMOS invertereffective capacitanceinterconnect loads
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Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance
Atsushi KUROKAWA Masanori HASHIMOTO Akira KASEBE Zhangcai HUANG Yun YANG Yasuaki INOUE Ryosuke INAGAKI Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3453-3462
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
Keyword: 
capacitance formulacapacitance calculationcapacitance extractioninterconnect capacitance
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A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads
Zhangcai HUANG Atsushi KUROKAWA Yasuaki INOUE Junfa MAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/10/01
Vol. E88-A  No. 10  pp. 2562-2569
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
Category: 
Keyword: 
static timing analysisgate delayCMOS invertereffective capacitanceinterconnect loads
 Summary | Full Text:PDF