IEICE Trans

Yuzo TAKAMATSU

Addressing Defect Coverage through Generating Test Vectors for Transistor Defects Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3128-3135 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verfication Keyword: test generation, transistor defects, stuck-at tests, defect coverage,
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Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3506-3513 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: fault simulation, test generation, stuck-open faults, stuck-at tests, defect coverage,
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A Method of Locating Open Faults on Incompletely Identified Pass/Fail Information Koji YAMAZAKI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 661-666 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: Fault Diagnosis Keyword: fault diagnosis, open fault, BIST, pass/fail information,
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Post-BIST Fault Diagnosis for Multiple Faults Hiroshi TAKAHASHI Yoshinobu HIGAMI Shuhei KADOYAMA Yuzo TAKAMATSU Koji YAMAZAKI Takashi AIKYO Yasuo SATO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 771-775 Type of Manuscript: Special Section LETTER (Special Section on Test and Verification of VLSIs) Category: Keyword: post-BIST fault diagnosis, multiple stuck-at faults, combinational circuits, pass/fail information,
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Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 690-699 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: Defect-Based Testing Keyword: transistor short, fault simulation, test generation, stuck-at test tool,
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Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information Yuzo TAKAMATSU Hiroshi TAKAHASHI Yoshinobu HIGAMI Takashi AIKYO Koji YAMAZAKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 675-682 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: Fault Diagnosis Keyword: diagnosis, fault model, fault location, fault simulation, combinational circuits, pass/fail information,
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On Finding Don't Cares in Test Sequences for Sequential Circuits Yoshinobu HIGAMI Seiji KAJIHARA Irith POMERANZ Shin-ya KOBAYASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/11/01 Vol. E89-D No. 11 pp. 2748-2755 Type of Manuscript: PAPER Category: Dependable Computing Keyword: test generation, don't care value, sequential circuit, stuck-at fault,
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Generation of Test Sequences with Low Power Dissipation for Sequential Circuits Yoshinobu HIGAMI Shin-ya KOBAYASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/03/01 Vol. E87-D No. 3 pp. 530-536 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSI) Category: Test Generation and Compaction Keyword: LSI testing, sequential circuit, test generation, low power dissipation, stuck-at fault,
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An Alternative Test Generation for Path Delay Faults by Using N_i-Detection Test Sets Hiroshi TAKAHASHI Kewal K. SALUJA Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/12/01 Vol. E86-D No. 12 pp. 2650-2658 Type of Manuscript: Special Section PAPER (Special Issue on Dependable Computing) Category: Test Keyword: test generation, path delay faults N-propagation test-pair set, combinational circuits,
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Diagnosing Crosstalk Faults in Sequential Circuits Using Fault Simulation Hiroshi TAKAHASHI Marong PHADOONGSIDHI Yoshinobu HIGAMI Kewal K. SALUJA Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/10/01 Vol. E85-D No. 10 pp. 1515-1525 Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI) Category: Test and Diagnosis for Timing Faults Keyword: diagnosis, crosstalk fault, fault simulation, sequential circuit,
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Design of C-Testable Modified-Booth Multipliers Kwame Osei BOATENG Hiroshi TAKAHASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2000/10/25 Vol. E83-D No. 10 pp. 1868-1878 Type of Manuscript: PAPER Category: Fault Tolerance Keyword: multiplier, modified Booth Algorithm, design for testability (DFT), C-testable design,
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Diagnosing Delay Faults in Combinational Circuits Under the Ambiguous Delay Model Kwame Osei BOATENG Hiroshi TAKAHASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/12/25 Vol. E82-D No. 12 pp. 1563-1571 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: combinational circuit, ambiguous delay model, multiple fault diagnosis, path-tracing method,
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A Method of Generating Tests with Linearity Property for Gate Delay Faults in Combinational Circuits Hiroshi TAKAHASHI Kwame Osei BOATENG Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/11/25 Vol. E82-D No. 11 pp. 1466-1473 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: combinational circuit, marginal chip, gate delay fault, test generation, test with linearity property,
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Multiple Gate Delay Fault Diagnosis Using Test-Pairs for Marginal Delays Kwame Osei BOATENG Hiroshi TAKAHASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/07/25 Vol. E81-D No. 7 pp. 706-715 Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI) Category: Fault Diagnosis Keyword: combinational circuit, fault diagnosis, multiple delay fault, diagnostic rules, path-tracing method, test-pairs for marginal delays,
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FOREWORD Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/07/25 Vol. E81-D No. 7 pp. 643-644 Type of Manuscript: FOREWORD Category: Keyword:
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A Method of Multiple Fault Diagnosis in Sequential Circuits by Sensitizing Sequence Pairs Nobuhiro YANAGIDA Hiroshi TAKAHASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/01/25 Vol. E80-D No. 1 pp. 28-37 Type of Manuscript: Special Section PAPER (Special Issue on Fault-Tolerant Computing) Category: Testing/Checking Keyword: sequential circuits, circuit level diagnosis, sensitizing sequence pairs, deduction algorithm, suspected/candidate faults,
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A Study for Testability of Redundant Faults in Combinational Circuits Using Delay Effects Xiangqiu YU Hiroshi TAKAHASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/07/25 Vol. E78-D No. 7 pp. 822-829 Type of Manuscript: Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems) Category: Keyword: test generation, combinational circuits, redundant faults, delay effect, extended seven-valued calculus,
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Improved Forward Test Generation of Sequential Circuits Using Variable-Length Time Frames Yuzo TAKAMATSU Taijiro OGAWA Hiroshi TAKAHASHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/07/25 Vol. E76-D No. 7 pp. 832-836 Type of Manuscript: Special Section LETTER (Special Issue on VLSI Testing and Testable Design) Category: Keyword: forward test generation, sequential circuits, variable-length time frames, state escaping,
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A Method of Generating Tests for Combinational Circuits with Multiple Faults Hiroshi TAKAHASHI Nobukage IUCHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1992/07/25 Vol. E75-D No. 4 pp. 569-576 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: multiple faults, combinational circuits, test generation, robust tests,
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Bit-Serial Squarer in Finite Fields with Characteristic 2 Masakatu MORII Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1990/08/25 Vol. E73-E No. 8 pp. 1314-1318 Type of Manuscript: LETTER Category: Information Theory and Coding Theory Keyword:
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