Yutaka TAMIYA


Efficient Multiplexer Networks for Field-Data Extractors and Their Evaluations
Koki ITO Kazushi KAWAMURA Yutaka TAMIYA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   
Publication Date: 2017/04/01
Vol. E100-A  No. 4  pp. 1015-1028
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
field-data extractormultiplexer networkpartitioningrotator
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Bi-Partitioning Based Multiplexer Network for Field-Data Extractors
Koki ITO Kazushi KAWAMURA Yutaka TAMIYA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7  pp. 1410-1414
Type of Manuscript:  Special Section LETTER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
multiplexer networkpartitioningfield-data extractor
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Robust Performance Optimization Using Padding Nodes and Separator Sets
Yutaka TAMIYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2739-2745
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Analysis
Keyword: 
timing optimizationseparator setnetwork flow algorithm
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Path Mapping: Delay Estimation for Technology Independent Synthesis
Yutaka TAMIYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10  pp. 1782-1788
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
technology independent synthesistechnology mappingdelay estimation
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LP Based Cell Selection with Constraints of Timing, Area, and Power Consumption
Yutaka TAMIYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/03/25
Vol. E78-A  No. 3  pp. 331-336
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems)
Category: VLSI Design Technology and CAD
Keyword: 
gate sizingtiming optimizationpower consumptionlinear programming
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