Yutaka SHINAGAWA


A 300 MHz Embedded Flash Memory with Pipeline Architecture and Offset-Free Sense Amplifiers for Dual-Core Automotive Microcontrollers
Shinya KAJIYAMA Masamichi FUJITO Hideo KASAI Makoto MIZUNO Takanori YAMAGUCHI Yutaka SHINAGAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/10/01
Vol. E92-C  No. 10  pp. 1258-1264
Type of Manuscript:  Special Section PAPER (Special Section on Hardware and Software Technologies on Advanced Microprocessors)
Category: 
Keyword: 
flash memorymicrocontrollerdual-coreshared ROMpipelinesense amplifier
 Summary | Full Text:PDF(1.6MB)