IEICE Trans

Yuta YAMATO

Reliability-Enhanced ECC-Based Memory Architecture Using In-Field Self-Repair Gian MAYUGA Yuta YAMATO Tomokazu YONEDA Yasuo SATO Michiko INOUE
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2016/10/01 Vol. E99-D No. 10 pp. 2591-2599 Type of Manuscript: PAPER Category: Dependable Computing Keyword: memory repair, memory reliability, in-field test and repair, ECC, in-field repair strategy, remapping,
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A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing Kohei MIYASE Ryota SAKAI Xiaoqing WEN Masao ASO Hiroshi FURUKAWA Yuta YAMATO Seiji KAJIHARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/09/01 Vol. E96-D No. 9 pp. 2003-2011 Type of Manuscript: Special Section PAPER (Special Section on Dependable Computing) Category: Keyword: at-speed testing, ATPG, IR-drop, test power reduction, low power test,
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Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing Kohei MIYASE Kenji NODA Hideaki ITO Kazumi HATAYAMA Takashi AIKYO Yuta YAMATO Hiroshi FURUKAWA Xiaoqing WEN Seiji KAJIHARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/06/01 Vol. E94-D No. 6 pp. 1216-1226 Type of Manuscript: PAPER Category: Dependable Computing Keyword: ATPG, X-bit, X-identification, X-filling,
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A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing Yuta YAMATO Xiaoqing WEN Kohei MIYASE Hiroshi FURUKAWA Seiji KAJIHARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/04/01 Vol. E94-D No. 4 pp. 833-840 Type of Manuscript: PAPER Category: Dependable Computing Keyword: X-filling, genetic algorithm, launch switching activity, IR-drop, at-speed scan testing,
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A Study of Capture-Safe Test Generation Flow for At-Speed Testing Kohei MIYASE Xiaoqing WEN Seiji KAJIHARA Yuta YAMATO Atsushi TAKASHIMA Hiroshi FURUKAWA Kenji NODA Hideaki ITO Kazumi HATAYAMA Takashi AIKYO Kewal K. SALUJA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/07/01 Vol. E93-A No. 7 pp. 1309-1318 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: at-speed scan testing, test generation, X-bit identification, X-filling, capture-safety checking,
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High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme Kohei MIYASE Xiaoqing WEN Hiroshi FURUKAWA Yuta YAMATO Seiji KAJIHARA Patrick GIRARD Laung-Terng WANG Mohammad TEHRANIPOOR
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/01/01 Vol. E93-D No. 1 pp. 2-9 Type of Manuscript: Special Section PAPER (Special Section on Test, Diagnosis and Verification of SOCs) Category: Keyword: power supply noise, test relaxation, X-filling, clock-gating, test compaction,
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A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits Yuta YAMATO Yusuke NAKAMURA Kohei MIYASE Xiaoqing WEN Seiji KAJIHARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 667-674 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: Fault Diagnosis Keyword: fault diagnosis, X-fault model, per-test, via,
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A Per-Test Fault Diagnosis Method Based on the X-Fault Model Xiaoqing WEN Seiji KAJIHARA Kohei MIYASE Yuta YAMATO Kewal K. SALUJA Laung-Terng WANG Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/11/01 Vol. E89-D No. 11 pp. 2756-2765 Type of Manuscript: PAPER Category: Dependable Computing Keyword: fault diagnosis, per-test, X-fault model,
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