Yusuke MATSUNAGA


A Test Pattern Compaction Method Using SAT-Based Fault Grouping
Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12  pp. 2302-2309
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
ATPGSATtest pattern
 Summary | Full Text:PDF(298.8KB)

Accelerating SAT-Based Boolean Matching for Heterogeneous FPGAs Using One-Hot Encoding and CEGAR Technique
Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7  pp. 1374-1380
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
logic synthesistechnology mappingFPGASAT
 Summary | Full Text:PDF(223.5KB)

Synthesis Algorithm for Parallel Index Generator
Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12  pp. 2451-2458
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
logic synthesisindex generation function
 Summary | Full Text:PDF(502.1KB)

An Exact Approach for GPC-Based Compressor Tree Synthesis
Taeko MATSUNAGA Shinji KIMURA Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2553-2560
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
compressor treegeneralized parallel counterinteger linear programmingarithmetic synthesis
 Summary | Full Text:PDF(850.4KB)

Multi-Operand Adder Synthesis Targeting FPGAs
Taeko MATSUNAGA Shinji KIMURA Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2579-2586
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
multi-operand addergeneralized parallel counterarithmetic synthesisFPGA
 Summary | Full Text:PDF(718KB)

Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAs
Taiga TAKATA Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3268-3275
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
FPGAtechnology mappingcut enumeration
 Summary | Full Text:PDF(340.2KB)

Character Projection Mask Set Optimization for Enhancing Throughput of MCC Projection Systems
Makoto SUGIHARA Yusuke MATSUNAGA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3451-3460
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
maskless lithographymulti-column-cellscharacter projectionvariable-shaped beamthroughput
 Summary | Full Text:PDF(754.9KB)

A Behavioral Synthesis Method with Special Functional Units
Tsuyoshi SADAKATA Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/04/01
Vol. E91-A  No. 4  pp. 1084-1091
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
Behavioral Synthesisschedulingallocationmodule selectionoperation chaining
 Summary | Full Text:PDF(236.8KB)

FOREWORD
Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12  pp. 2649-2650
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(53.5KB)

Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders
Taeko MATSUNAGA Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12  pp. 2770-2777
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis and Verification
Keyword: 
parallel prefix adderarithmetic synthesisdynamic programming
 Summary | Full Text:PDF(308.7KB)

Technology Mapping Technique for Increasing Throughput of Character Projection Lithography
Makoto SUGIHARA Kenta NAKAMURA Yusuke MATSUNAGA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/05/01
Vol. E90-C  No. 5  pp. 1012-1020
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Lithography-Related Techniques
Keyword: 
maskless lithographycharacter projectionvariable-shaped beamtechnology mappingthroughput
 Summary | Full Text:PDF(715.6KB)

FOREWORD
Yusuke MATSUNAGA  
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/04/01
Vol. E90-A  No. 4  pp. 705-706
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(53.3KB)

A Simultaneous Module Selection, Scheduling, and Allocation Method Considering Operation Chaining with Multi-Functional Units
Tsuyoshi SADAKATA Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/04/01
Vol. E90-A  No. 4  pp. 792-799
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
high-level synthesisschedulingallocationmodule selectionoperation chaininginteger linear programming
 Summary | Full Text:PDF(215.1KB)

Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment
Makoto SUGIHARA Taiga TAKATA Kenta NAKAMURA Ryoichi INANAMI Hiroaki HAYASHI Katsumi KISHIMOTO Tetsuya HASEBE Yukihiro KAWANO Yusuke MATSUNAGA Kazuaki MURAKAMI Katsuya OKUMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3  pp. 377-383
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: CAD
Keyword: 
cell librarycharacter projectionelectron beamEB shotsthroughputoptimizationinteger linear programming
 Summary | Full Text:PDF(427.7KB)

Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints
Makoto SUGIHARA Kazuaki MURAKAMI Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3174-3184
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
core-based designSOCTAMtest architecturefloorplantest scheduling
 Summary | Full Text:PDF(332.4KB)

An Efficient Algorithm Finding Simple Disjoint Decompositions Using BDDs
Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12  pp. 2715-2724
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
functional decompositionBDDslogic synthesisFPGA
 Summary | Full Text:PDF(295.2KB)

Robust Heuristics for Multi-Level Logic Simplification Considering Local Circuit Structure
Qiang ZHU Yusuke MATSUNAGA Shinji KIMURA Katsumasa WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2520-2527
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
multi-level logic simplificationsatisfiability don't caresobservability don't caresadaptive subnetwork
 Summary | Full Text:PDF(325.8KB)

An lterative Improvement Method for State Minimization of Incompletely Specified Finite State Machines
Hiroyuki HIGUCHI Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/10/25
Vol. E80-D  No. 10  pp. 993-1000
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Design
Keyword: 
state minimizationstate reductionfinite state machinesbinate covering problemcompatible sets
 Summary | Full Text:PDF(643.2KB)

Phase Optimization in Technology Mapping
Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12  pp. 1735-1741
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
logic synthesistechnology mappingphase optimizationbinary decision diagrams
 Summary | Full Text:PDF(514.1KB)

A New Algorithm for Boolean Matching Utilizing Structural Information
Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/03/25
Vol. E78-D  No. 3  pp. 219-223
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Synthesis
Keyword: 
logic synthesistechnology mappingBoolean matchingbinary decision diagrams
 Summary | Full Text:PDF(380.7KB)

MINT--An Exact Algorithm for Finding Minimum Test Set--
Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10  pp. 1652-1658
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
test pattern generationminimum test setbinary decision diagramminimum set covering problem
 Summary | Full Text:PDF(561.6KB)

Enhanced Unique Sensitization for Efficient Test Generation
Yusuke MATSUNAGA Masahiro FUJITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/09/25
Vol. E76-D  No. 9  pp. 1114-1120
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Test
Keyword: 
computer hardware and disigntesting and verification
 Summary | Full Text:PDF(619.2KB)