Yusuke KANNO

Soft-Error-Tolerant Dual-Modular-Redundancy Architecture with Repair and Retry Scheme for Memory-Control Circuit on FPGA
Makoto SAEN Tadanobu TOBA Yusuke KANNO 
Publication:   
Publication Date: 2017/04/01
Vol. E100-C  No. 4  pp. 382-390
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
FPGA, soft-error tolerance, memory controller, configuration RAM, 
 Summary | Full Text:PDF
A Method for Measuring of RTN by Boosting Word-Line Voltage in 6-Tr-SRAMs
Goichi ONO Yuki MORI Michiaki NAKAYAMA Yusuke KANNO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/03/01
Vol. E97-C  No. 3  pp. 215-221
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
random telegraph noise, static random access memory, 
 Summary | Full Text:PDF
µI/O Architecture: A Power-Aware Interconnect Circuit Design for SoC and SiP
Yusuke KANNO Hiroyuki MIZUNO Nobuhiro OODAIRA Yoshihiko YASU Kazumasa YANAGISAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4  pp. 589-597
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
low-cost, System-on-Chip, SoC, System-in-Package, SiP, hierarchical I/O design, signal-level converter, signal wall function, low-power, interconnect circuit, 
 Summary | Full Text:PDF