IEICE Trans

Yukihiro NAKAMURA

Hardware Accelerator for Run-Time Learning Adopted in Object Recognition with Cascade Particle Filter Hiroki SUGANO Hiroyuki OCHI Yukihiro NAKAMURA Ryusuke MIYAMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/11/01 Vol. E92-A No. 11 pp. 2801-2808 Type of Manuscript: Special Section PAPER (Special Section on Smart Multimedia & Communication Systems) Category: Image Processing Keyword: Cascade Particle Filter, hardware accelerator, embedded systems, real-time processing,
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Efficient Memory Organization Framework for JPEG2000 Entropy Codec Hiroki SUGANO Takahiko MASUZAKI Hiroshi TSUTSUI Takao ONOYE Hiroyuki OCHI Yukihiro NAKAMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/08/01 Vol. E92-A No. 8 pp. 1970-1977 Type of Manuscript: Special Section PAPER (Special Section on Signal Processing) Category: Realization Keyword: JPEG2000, entropy codec, hardware, memory organization,
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Autonomous Repair Fault Tolerant Dynamic Reconfigurable Device Kentaro NAKAHARA Shin'ichi KOUYAMA Tomonori IZUMI Hiroyuki OCHI Yukihiro NAKAMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3612-3621 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Embedded, Real-Time and Reconfigurable Systems Keyword: fault tolerance, dependable, FPGA, reconfigurable device, soft error,
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Evaluation of Reliable Multicast Applications for Large-Scale Contents Delivery Teruji SHIROSHITA Shingo KINOSHITA Takahiko NAGATA Tetsuo SANO Yukihiro NAKAMURA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2007/10/01 Vol. E90-B No. 10 pp. 2738-2745 Type of Manuscript: Special Section PAPER (Special Section on New Challenge for Internet Technology and its Architecture) Category: Keyword: contents delivery, reliable multicast, communication protocol, large-scale system,
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A Simulation Platform for Designing Cell-Array-Based Self-Reconfigurable Architecture Shin'ichi KOUYAMA Tomonori IZUMI Hiroyuki OCHI Yukihiro NAKAMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/04/01 Vol. E90-A No. 4 pp. 784-791 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: self-reconfiguration, evaluation of architecture, model of architecture, simulation,
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Stochastic Pedestrian Tracking Based on 6-Stick Skeleton Model Ryusuke MIYAMOTO Jumpei ASHIDA Hiroshi TSUTSUI Yukihiro NAKAMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/03/01 Vol. E90-A No. 3 pp. 606-617 Type of Manuscript: Special Section PAPER (Special Section on Multimedia and Mobile Signal Processing) Category: Image Keyword: pedestrian tracking, particle filter, skeleton, distance transformation,
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Efficient 3-D Sound Movement with Time-Varying IIR Filters Kosuke TSUJINO Wataru KOBAYASHI Takao ONOYE Yukihiro NAKAMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/03/01 Vol. E90-A No. 3 pp. 618-625 Type of Manuscript: Special Section PAPER (Special Section on Multimedia and Mobile Signal Processing) Category: Speech/Audio Processing Keyword: head-related transfer function, binaural synthesis, pole-zero modeling,time-varying filter,
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Fault Tolerant Dynamic Reconfigurable Device Based on EDAC with Rollback Kentaro NAKAHARA Shin'ichi KOUYAMA Tomonori IZUMI Hiroyuki OCHI Yukihiro NAKAMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3652-3658 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Architecture Keyword: fault tolerance, dependable, dynamic reconfigurable,
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Design of Realtime 3-D Sound Processing System Kosuke TSUJINO Kazuhiko FURUYA Wataru KOBAYASHI Tomonori IZUMI Takao ONOYE Yukihiro NAKAMURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/05/01 Vol. E88-D No. 5 pp. 954-962 Type of Manuscript: Special Section PAPER (Special Section on Cyberworlds) Category: Keyword: 3-D sound, virtual reality, system implementation,
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An Integrated Approach of Variable Ordering and Logic Mapping into LUT-Array-Based PLD Tomonori IZUMI Shin'ichi KOUYAMA Hiroyuki OCHI Yukihiro NAKAMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/04/01 Vol. E88-A No. 4 pp. 907-914 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: reconfigurable system, design technology, logic synthesis, variable ordering, look-up table,
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Design Tools and Trial Designs for PCA-Chip2 Takuya OKAMOTO Takafumi YUASA Tomonori IZUMI Takao ONOYE Yukihiro NAKAMURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/05/01 Vol. E86-D No. 5 pp. 868-871 Type of Manuscript: Special Section LETTER (Special Issue on Reconfigurable Computing) Category: Keyword: Plastic Cell Architecture, reconfigurable logic, design automation, computer aided design,
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LUT-Array-Based PLD and Synthesis Approach Based on Sum of Generalized Complex Terms Expression Hiroshi TSUTSUI Akihiko TOMITA Shigenori SUGIMOTO Kazuhisa SAKAI Tomonori IZUMI Takao ONOYE Yukihiro NAKAMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 pp. 2681-2689 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: FPGA Systhesis Keyword: reconfigurable logic, programmable logic, system architecture and design, logic synthesis, sum of products,
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Array-Based Mapping Algorithm of Logic Functions into Plastic Cell Architecture Tomonori IZUMI Ryuji KAN Yukihiro NAKAMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/25 Vol. E83-A No. 12 pp. 2538-2544 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: plastic cell architecture, reconfigurable logic, technology mapping, layout,
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FOREWORD Yukihiro NAKAMURA Takashi KAMBE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/25 Vol. E83-A No. 12 pp. 2399-2399 Type of Manuscript: FOREWORD Category: Keyword:
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Inverter Reduction Algorithm for Super Fine-Grain Parallel Processing Hideyuki ITO Kouichi NAGAMI Tsunemichi SHIOZAWA Kiyoshi OGURI Yukihiro NAKAMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/03/25 Vol. E80-A No. 3 pp. 487-493 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems) Category: Keyword: super fine-grain parallel processing, FPGA, high level synthesize PARTHENON, inverter reduction, dynamical system,
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High-Level Synthesis Design at NTT Systems Labs Yukihiro NAKAMURA Kiyoshi OGURI Akira NAGOYA Mitsuteru YUKISHITA Ryo NOMURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/09/25 Vol. E76-D No. 9 pp. 1047-1054 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: High-Level Design Keyword: computer-hardware and disign,
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Algorithms for Multiplexers Assignment after Scheduling and Allocation Steps Hiroshi SEKIGAWA Kiyoshi OGURI Ryo NOMURA Yukihiro NAKAMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/10/25 Vol. E75-A No. 10 pp. 1202-1211 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: computer hardware and design,
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