Yukihide KOHIRA


Clustering Method for Reduction of Area and Power Consumption on Post-Silicon Delay Tuning
Kota MUROI Hayato MASHIKO Yukihide KOHIRA 
Publication:   
Publication Date: 2019/07/01
Vol. E102-A  No. 7  pp. 894-903
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
post-silicon delay tuningprogrammable delay elementyield improvementpower consumption reduction
 Summary | Full Text:PDF(1.1MB)

Technology Mapping Method Using Integer Linear Programming for Low Power Consumption and High Performance in General-Synchronous Framework
Junki KAWAGUCHI Hayato MASHIKO Yukihide KOHIRA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7  pp. 1366-1373
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
general-synchronous frameworktechnology mappinginteger linear programming
 Summary | Full Text:PDF(753.4KB)

A Tuning Method of Programmable Delay Element with an Ordered Finite Set of Delays for Yield Improvement
Hayato MASHIKO Yukihide KOHIRA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12  pp. 2443-2450
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
delay variationtiming violationyieldprogrammable delay element
 Summary | Full Text:PDF(1.1MB)

2-SAT Based Linear Time Optimum Two-Domain Clock Skew Scheduling in General-Synchronous Framework
Yukihide KOHIRA Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12  pp. 2459-2466
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
general-synchronous frameworkmulti-domain clock skew schedulingtwo-domain clock skew scheduling2-SAT
 Summary | Full Text:PDF(430.7KB)

An Effective Overlap Removable Objective for Analytical Placement
Syota KUWABARA Yukihide KOHIRA Yasuhiro TAKASHIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/06/01
Vol. E96-A  No. 6  pp. 1348-1356
Type of Manuscript:  Special Section PAPER (Special Section on Circuit, System, and Computer Technologies)
Category: 
Keyword: 
analytical placementminimization of overlap areaoverlap evaluation
 Summary | Full Text:PDF(1.2MB)

Single-Layer Trunk Routing Using Minimal 45-Degree Lines
Kyosuke SHINODA Yukihide KOHIRA Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2510-2518
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
printed circuit boardplanar routingtrunk routingrouting density45-degree line
 Summary | Full Text:PDF(1.4MB)

CAFE Router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles
Yukihide KOHIRA Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12  pp. 2380-2388
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
PCB routinglength-matching routingtrunk routing
 Summary | Full Text:PDF(1.9MB)

A Fast Longer Path Algorithm for Routing Grid with Obstacles Using Biconnectivity Based Length Upper Bound
Yukihide KOHIRA Suguru SUEHIRO Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 2971-2978
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Desing
Keyword: 
routing design of PCBlonger path algorithmupper bound of wire length
 Summary | Full Text:PDF(751.5KB)

MILP-Based Efficient Routing Method with Restricted Route Structure for 2-Layer Ball Grid Array Packages
Yoichi TOMIOKA Yoshiaki KURATA Yukihide KOHIRA Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 2998-3006
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Desing
Keyword: 
ball grid arraymonotonicnearest via assignmentpackage routingradiate
 Summary | Full Text:PDF(480.7KB)

Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework
Yukihide KOHIRA Shuhei TANI Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/04/01
Vol. E92-A  No. 4  pp. 1106-1114
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
delay insertionclock schedulinggeneral-synchronous framework
 Summary | Full Text:PDF(835.2KB)

A Fast Clock Scheduling for Peak Power Reduction in LSI
Yosuke TAKAHASHI Yukihide KOHIRA Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3803-3811
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
clock schedulinggeneral-synchronous frameworkpeak power reductionpeak power wave estimation
 Summary | Full Text:PDF(825.6KB)

A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework
Yukihide KOHIRA Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/10/01
Vol. E91-A  No. 10  pp. 3030-3037
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
register relocationretimingclock schedulinggeneral-synchronous framework
 Summary | Full Text:PDF(440.8KB)

Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization
Yukihide KOHIRA Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/04/01
Vol. E90-A  No. 4  pp. 800-807
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
register relocationretimingclock period minimizationgeneralized synchronous framework
 Summary | Full Text:PDF(357KB)

Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion
Yukihide KOHIRA Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A  No. 4  pp. 892-898
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
delay insertionclock period minimizationsemi-synchronous circuitdelay-slackdelay-demand
 Summary | Full Text:PDF(277.9KB)