Yuchun MA


Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs
Kan WANG Sheqin DONG Yuchun MA Yu WANG Xianlong HONG Jason CONG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2490-2498
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
leakage powerTSVdelay-power-temperature dependence
 Summary | Full Text:PDF(2.7MB)

Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation
Yuchun MA Xin LI Yu WANG Xianlong HONG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 2979-2989
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Desing
Keyword: 
3D ICsincremental floorplanningthermalMILP
 Summary | Full Text:PDF(537.2KB)

VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation
Yuchun MA Xianlong HONG Sheqin DONG Yici CAI Chung-Kuan CHENG Jun GU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2697-2704
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Layout
Keyword: 
floorplancorner block listsimulated annealingboundary constraints
 Summary | Full Text:PDF(2.1MB)