Yu-Liang WU


On Structural Analysis and Efficiency for Graph-Based Rewiring Techniques
Fu-Shing CHIM Tak-Kei LAM Yu-Liang WU Hongbing FAN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2853-2865
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
design automationATPGimplicationredundancy identificationgraph-based rewiringvery-large-scale integration
 Summary | Full Text:PDF

An Efficient Exact Router for Hyper-Universal Switching Box
Jiping LIU Hongbing FAN Dinah de PORTO Yu-Liang WU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/06/01
Vol. E86-A  No. 6  pp. 1430-1436
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 2002 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2002))
Category: 
Keyword: 
FPGA routerhyper-universal switch box
 Summary | Full Text:PDF

Accelerating Logic Rewiring Using Implication Analysis Tree
Chin-Ngai SZE Wangning LONG Yu-Liang WU Jinian BIAN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12  pp. 2725-2736
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
alternative wirelogic transformationlogic synthesis
 Summary | Full Text:PDF

A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks
Yu-Liang WU Wangning LONG Hongbing FAN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/06/25
Vol. E83-A  No. 6  pp. 1131-1137
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99))
Category: 
Keyword: 
rewiringlogic synthesiscircuit minimizationredundancy
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On Improved FPGA Greedy Routing Architectures
Yu-Liang WU Douglas CHANG Malgorzata MAREK-SADOWSKA Shuji TSUKIYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2485-2491
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Layout Optimization
Keyword: 
FPGA architectureFPGA Greedy routing architecture
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On Regular Segmented 2-D FPGA Routing
Yu-Liang WU Malgorzata MAREK-SADOWSKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10  pp. 1871-1877
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FPGA routingFPGA architechtureFPGA segmented routing
 Summary | Full Text:PDF