Yu-Cheng FAN

Boundary Scan Test Scheme for IP Core Identification via Watermarking
Yu-Cheng FAN Hen-Wai TSAO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7  pp. 1397-1400
Type of Manuscript:  Special Section LETTER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Programmable Logic, VLSI, CAD and Layout
boundary scan test scheme (BSTS)intellectual property (IP) identificationsystem on a chip (SOC)VLSI designwatermarking
 Summary | Full Text:PDF(825.5KB)