IEICE Trans

Young-Chan JANG

A 3Gbps/Lane MIPI D-PHY Transmission Buffer Chip Pil-Ho LEE Young-Chan JANG
Publication: Publication Date: 2019/06/01 Vol. E102-A No. 6 pp. 783-787 Type of Manuscript: Special Section LETTER (Special Section on Circuits and Systems) Category: Keyword: transmission buffer chip, LVDS, SLVS, MIPI D-PHY, FPGA-based frame generator,
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A 10 Gbps D-PHY Transmitter Bridge Chip for FPGA-Based Frame Generator Supporting MIPI DSI of Mobile Display Ho-Seong KIM Pil-Ho LEE Jin-Wook HAN Seung-Hun SHIN Seung-Wuk BAEK Doo-Ill PARK Yongkyu SEO Young-Chan JANG
Publication: Publication Date: 2017/11/01 Vol. E100-C No. 11 pp. 1035-1038 Type of Manuscript: BRIEF PAPER Category: Keyword: transmitter bridge chip, MIPI D-PHY, DSI, FPGA-based frame generator, phase-locked loop,
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A 10-bit 20-MS/s Asynchronous SAR ADC with Meta-Stability Detector Using Replica Comparators Sang-Min PARK Yeon-Ho JEONG Yu-Jeong HWANG Pil-Ho LEE Yeong-Woong KIM Jisu SON Han-Yeol LEE Young-Chan JANG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2016/06/01 Vol. E99-C No. 6 pp. 651-654 Type of Manuscript: BRIEF PAPER Category: Keyword: asynchronous successive approximation register, analog-to-digital converter, meta-stability detector, replica comparator,
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An On-Chip Monitoring Circuit with 51-Phase PLL-Based Frequency Synthesizer for 8-Gb/s ODR Single-Ended Signaling Integrity Analysis Pil-Ho LEE Yu-Jeong HWANG Han-Yeol LEE Hyun-Bae LEE Young-Chan JANG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2016/04/01 Vol. E99-C No. 4 pp. 440-443 Type of Manuscript: BRIEF PAPER Category: Keyword: on-chip monitoring circuit, chip-to-chip interface, analog-to-digital converter, phase-locked loop-based frequency synthesizer, sub-sampling,
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A 2-Gb/s CMOS SLVS Transmitter with Asymmetric Impedance Calibration for Mobile Interfaces Kwang-Hun LEE Young-Chan JANG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/08/01 Vol. E97-C No. 8 pp. 837-840 Type of Manuscript: BRIEF PAPER Category: Electronic Circuits Keyword: scalable low voltage signaling, transmitter, impedance calibration, common mode voltage,
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A 10-bit CMOS Digital-to-Analog Converter with Compact Size for Display Applications Mungyu KIM Hoon-Ju CHUNG Young-Chan JANG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/06/01 Vol. E97-C No. 6 pp. 519-525 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: digital-to-analog converter, resistor string, logarithmic time interpolator, low-pass filter, decoder,
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A 125MHz 64-Phase Delay-Locked Loop with Coarse-Locking Circuit Independent of Duty Cycle Pil-Ho LEE Hyun Bae LEE Young-Chan JANG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/05/01 Vol. E97-C No. 5 pp. 463-467 Type of Manuscript: BRIEF PAPER Category: Integrated Electronics Keyword: multi-phase DLL, harmonic lock, coarse-locking circuit, initial phase detector, duty cycle,
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An 8-Bit 100-kS/s CMOS Single-Ended SA ADC for 88 Point EEG/MEG Acquisition System Ji-Hun EO Yeon-Ho JEONG Young-Chan JANG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/02/01 Vol. E96-A No. 2 pp. 453-458 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: successive approximation, analog-to-digital converter, time-domain comparator, daisy channel,
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Mirrored Serpentine Microstrip Lines for Reduction of Far-End Crosstalk Hyun Bae LEE Young-Chan JANG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/06/01 Vol. E95-C No. 6 pp. 1086-1088 Type of Manuscript: BRIEF PAPER Category: Keyword: far-end crosstalk, mirrored serpentine microstrip line, high-speed digital signaling, time domain reflectometry,
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A 1 V 200 kS/s 10-bit Successive Approximation ADC for a Sensor Interface Ji-Hun EO Sang-Hun KIM Young-Chan JANG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/11/01 Vol. E94-C No. 11 pp. 1798-1801 Type of Manuscript: BRIEF PAPER Category: Electronic Circuits Keyword: successive approximation, analog-to-digital converter, split-capacitor-based digital-to-analog converter, time-domain comparator,
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A Bootstrapped Analog Switch with Constant On-Resistance Sang-hun KIM Yong-Hwan LEE Hoon-Ju CHUNG Young-Chan JANG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/06/01 Vol. E94-C No. 6 pp. 1069-1071 Type of Manuscript: BRIEF PAPER Category: Keyword: bootstrapped analog switch, input-sampling switch, analog-to-digital converter, on-resistance,
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A Self-Calibrating Per-Pin Phase Adjuster for Source Synchronous Double Data Rate Signaling in Parallel Interface Young-Chan JANG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/02/01 Vol. E94-A No. 2 pp. 633-638 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: phase adjuster, phase skew, source synchronous double data rate signaling, time-domain reflectometry,
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A Swing Level Controlled Transmitter for Single-Ended Signaling with Center-Tapped Termination Young-Chan JANG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/06/01 Vol. E93-C No. 6 pp. 861-863 Type of Manuscript: BRIEF PAPER Category: Keyword: transmitter, source termination, output impedance, single-ended signaling, diagnostic mode, swing level control,
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An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator Young-Chan JANG Jun-Hyun BAE Sang-Hune PARK Jae-Yoon SIM Hong-June PARK
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/06/01 Vol. E90-C No. 6 pp. 1156-1164 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: flash ADC, time-interleaving, phase-locked-loop, digital phase adjuster, digital duty cycle corrector,
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An 8-GS/s 4-Bit 340 mW CMOS Time Interleaved Flash Analog-to-Digital Converter Young-Chan JANG Sang-Hune PARK Seung-Chan HEO Hong-June PARK
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/02/01 Vol. E87-A No. 2 pp. 350-356 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: analog-to-digital converter, time interleaved flash converter, resistor averaging, distributed track-and-hold, phase locked loop,
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An 8-Bit 200 MS/s CMOS Folding/Interpolating Analog-to-Digital Converter Seung-Chan HEO Young-Chan JANG Sang-Hune PARK Hong-June PARK
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/04/01 Vol. E86-C No. 4 pp. 676-681 Type of Manuscript: LETTER Category: Electronic Circuits Keyword: analog-to-digital converter (ADC), resistor averaging, folding, interpolating, differential logic,
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