Young Hwan KIM

Accelerating Relaxation Using Dynamic Error Prediction
Hong Bo CHE Jin Wook KIM Tae Il BAE Young Hwan KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/02/01
Vol. E92-A  No. 2  pp. 648-651
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
circuit simulation, relaxation method, acceleration scheme, dynamic error prediction, 
 Summary | Full Text:PDF(323.3KB)
Realizable Reduction of RC Networks with Current Sources for Dynamic IR-Drop Analysis of Power Networks of SoCs
Hong Bo CHE Hyoun Soo PARK Jin Wook KIM Young Hwan KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/02/01
Vol. E92-A  No. 2  pp. 475-480
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
IR-drop analysis, RC network, network reduction, circuit simulation, perturbation theory, 
 Summary | Full Text:PDF(642.6KB)
New Gate Models for Gate-Level Delay Calculation under Crosstalk Effects
Tae Il BAE Jin Wook KIM Young Hwan KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3488-3496
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
crosstalk, gate model, delay calculation, timing analysis, 
 Summary | Full Text:PDF(1.9MB)
Timing Criticality for Timing Yield Optimization
Hyoun Soo PARK Wook KIM Dai Joon HYUN Young Hwan KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3497-3505
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
block-based SSTA, timing yield optimization, timing criticality, critical path identification, 
 Summary | Full Text:PDF(1.2MB)
Image Adaptive Incremental Subfield Coding for Plasma Display Panels
Myung Jin PARK Hyoun Soo PARK Young Hwan KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/11/01
Vol. E90-C  No. 11  pp. 2100-2104
Type of Manuscript:  Special Section LETTER (Special Section on Electronic Displays)
Category: 
Keyword: 
plasma display panel, subfield, false contour noise, halftone noise, incremental subfield coding method, 
 Summary | Full Text:PDF(688.8KB)
Symmetric Discharge Logic against Differential Power Analysis
Jong Suk LEE Jae Woon LEE Young Hwan KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/01/01
Vol. E90-A  No. 1  pp. 234-240
Type of Manuscript:  Special Section LETTER (Special Section on Cryptography and Information Security)
Category: 
Keyword: 
symmetric discharge logic, SDL, smart card, differential power analysis, DPA, 
 Summary | Full Text:PDF(325.5KB)
Image-Dependent Code Optimization to Improve Motion Picture Quality of Plasma Displays
Jong Suk LEE Bong Seok KANG Young Hwan KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/10/01
Vol. E89-C  No. 10  pp. 1400-1405
Type of Manuscript:  Special Section LETTER (Special Section on Electronic Displays)
Category: 
Keyword: 
plasma display panel, dynamic false contour, halftone, 
 Summary | Full Text:PDF(625.5KB)
Level Converting Flip-Flops for High-Speed and Low-Power Applications
Hyoun Soo PARK Bong Hyun LEE Young Hwan KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/06/01
Vol. E89-A  No. 6  pp. 1740-1743
Type of Manuscript:  Special Section LETTER (Special Section on Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2005))
Category: 
Keyword: 
multi-VDD system, multiple supply voltages, level conversion, flip-flop, 
 Summary | Full Text:PDF(981.7KB)
Clock-Free MTCMOS Flip-Flops with High Speed and Low Power
Bong Hyun LEE Young Hwan KIM Kwang-Ok JEONG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/06/01
Vol. E88-A  No. 6  pp. 1416-1424
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 2004 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2004))
Category: 
Keyword: 
flip-flop, MTCMOS, multithreshold-voltage CMOS, 
 Summary | Full Text:PDF(760.8KB)
Power Modeling of Synthesizable Soft Macros
Kyung Tae DO Yang Hyo KIM Young Hwan KIM Jung Yun CHOI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3091-3099
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
parameterized power model, synthesizable macro, RTL design, 
 Summary | Full Text:PDF(2.7MB)
DEMI: A Delay Minimization Algorithm for Cell-Based Digital VLSI Design
Tae Hoon KIM Young Hwan KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/03/25
Vol. E82-A  No. 3  pp. 504-511
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
delay minimization, cell-based design, critical path analysis, 
 Summary | Full Text:PDF(229.9KB)
Efficient Timing Verification of Latch-Synchronized Systems
Sang-Yeol HAN Young Hwan KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/09/25
Vol. E80-A  No. 9  pp. 1676-1683
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
VLSI design, synchronous elements, critical path analysis, timing error, 
 Summary | Full Text:PDF(622.9KB)