Yoshiyuki NAKAMURA


Effect of BIST Pretest on IC Defect Level
Yoshiyuki NAKAMURA Jacob SAVIR Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/10/01
Vol. E89-D  No. 10  pp. 2626-2636
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
BISTfault coveragedefect level
 Summary | Full Text:PDF

Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch
Yoshiyuki NAKAMURA Thomas CLOUQUEUR Kewal K. SALUJA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/03/01
Vol. E89-D  No. 3  pp. 1165-1172
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
BISTfault diagnosiserror identificationat-speed testlow speed tester
 Summary | Full Text:PDF

Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST
Yoshiyuki NAKAMURA Jacob SAVIR Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/06/01
Vol. E88-D  No. 6  pp. 1210-1216
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
BISTfault coveragedefect level
 Summary | Full Text:PDF