Yoshiyuki HARAGUCHI


A 4-Mb SRAM Using a New Hierarchical Bit Line Organization Utilizing a T-Shaped Bit Line for a Small Sized Die
Yoshiyuki HARAGUCHI Toshihiko HIROSE Motomu UKITA Tomohisa WADA Masanao EINO Minoru SAITO Michihiro YAMADA Akihiko YASUOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6  pp. 743-749
Type of Manuscript:  Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Static RAMs
Keyword: 
integrated electronicshigh density SRAMhierarchical bit line organizationT-shaged bit line
 Summary | Full Text:PDF(796.2KB)

An Analysis of Substrate Current in Memory Cell for ULSI SRAM
Yoshiyuki HARAGUCHI Shuji MURAKAMI Yasumasa NISHIMURA Kenji ANAMI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/11/25
Vol. E73-E  No. 11  pp. 1861-1862
Type of Manuscript:  Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE)
Category: Integrated Circuits
Keyword: 
 Summary | Full Text:PDF(133.6KB)