Yoshio MATSUDA


A 100-MHz 51.2-Gb/s Packet Lookup Engine with Automatic Table Update Function
Kousuke IMAMURA Ryota HONDA Yoshifumi KAWAMURA Naoki MIURA Masami URANO Satoshi SHIGEMATSU Tetsuya MATSUMURA Yoshio MATSUDA 
Publication:   
Publication Date: 2017/10/01
Vol. E100-A  No. 10  pp. 2123-2134
Type of Manuscript:  PAPER
Category: Communication Theory and Signals
Keyword: 
lookup enginepacket inspectionmismatch detectionhash searchrule registrationrule deletion
 Summary | Full Text:PDF(3.2MB)

A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals
Yoshifumi KAWAMURA Naoya OKADA Yoshio MATSUDA Tetsuya MATSUMURA Hiroshi MAKINO Kazutami ARIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/05/01
Vol. E99-A  No. 5  pp. 917-928
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
FPGAMCU peripheralsfield programmable devicessequencerSRAM
 Summary | Full Text:PDF(2.9MB)

A VGA 30 fps Affine Motion Model Estimation VLSI for Real-Time Video Segmentation
Yoshiki YUNBE Masayuki MIYAMA Yoshio MATSUDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/12/01
Vol. E93-D  No. 12  pp. 3284-3293
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
affine motion modelmotion estimationvideo segmentationreal-time processingVLSIFPGA
 Summary | Full Text:PDF(2.1MB)

A Complete Charge Recycling TCAM with Checkerboard Array Arrangement for Low Power Applications
Katsumi DOSAKA Daisuke OGAWA Takahito KUSUMOTO Masayuki MIYAMA Yoshio MATSUDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/05/01
Vol. E93-C  No. 5  pp. 685-695
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
TCAMcharge recyclinglow powerlow noiselow operating current
 Summary | Full Text:PDF(4.3MB)

A 158 MS/s JPEG 2000 Codec with a Bit-Plane and Pass Parallel Embedded Block Coder for Low Delay Image Transmission
Masayuki MIYAMA Yuusuke INOIE Takafumi KASUGA Ryouichi INADA Masashi NAKAO Yoshio MATSUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/08/01
Vol. E91-A  No. 8  pp. 2025-2034
Type of Manuscript:  Special Section PAPER (Special Section on Signal Processing)
Category: 
Keyword: 
JPEG 2000EBCOTVLSIlow delayimage transmission
 Summary | Full Text:PDF(1.5MB)

A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition
Yuichiro MURACHI Yuki FUKUYAMA Ryo YAMAMOTO Junichi MIYAKOSHI Hiroshi KAWAGUCHI Hajime ISHIHARA Masayuki MIYAMA Yoshio MATSUDA Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 457-464
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
optical flowreal-time video recognitionVLSI processor
 Summary | Full Text:PDF(1.2MB)

The Maximum Operating Region in SiGe HBTs for RF Power Amplifiers
Akira INOUE Shigenori NAKATSUKA Takahide ISHIKAWA Yoshio MATSUDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/05/01
Vol. E87-C  No. 5  pp. 714-719
Type of Manuscript:  Special Section PAPER (Special Section on Advances in Characterization and Measurement Technologies for Microwave and Millimeter-Wave Materials, Devices and Circuits)
Category: Active Devices and Circuits
Keyword: 
maximum operating regionmeasurementwaveformSiGepower amplifierHBT
 Summary | Full Text:PDF(726.3KB)

A Low Standby Current DSP Core Using Improved ABC-MT-CMOS with Charge Pump Circuit
Hiromi NOTANI Masayuki KOYAMA Ryuji MANO Hiroshi MAKINO Yoshio MATSUDA Osamu TOMISAWA Shuhei IWADE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4  pp. 597-603
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Circuit Design
Keyword: 
low powerstandby currentbackgate controlMT-CMOS
 Summary | Full Text:PDF(829.6KB)

Physical Design Methodology for On-Chip 64-Mb DRAM MPEG-2 Encoding with a Multimedia Processor
Hidehiro TAKATA Rei AKIYAMA Tadao YAMANAKA Haruyuki OHKUMA Yasue SUETSUGU Toshihiro KANAOKA Satoshi KUMAKI Kazuya ISHIHARA Atsuo HANAMI Tetsuya MATSUMURA Tetsuya WATANABE Yoshihide AJIOKA Yoshio MATSUDA Syuhei IWADE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2  pp. 368-374
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: Product Designs
Keyword: 
multimedia processorclock skewcross-talk noiseIR dropMPEG-2 encoder
 Summary | Full Text:PDF(1.6MB)

Novel VLIW Code Compaction Method for a 3D Geometry Processor
Hiroaki SUZUKI Hiroyuki KAWAI Hiroshi MAKINO Yoshio MATSUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2885-2893
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
VLIWcode compactionASSP3D geometry processorcomputer graphics
 Summary | Full Text:PDF(1.5MB)

A 250 MHz Dual Port Cursor RAM Using Dynamic Data Alignment Architecture
Yasunobu NAKASE Hiroyuki KONO Yoshio MATSUDA Hisanori HAMANO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/11/25
Vol. E81-C  No. 11  pp. 1750-1756
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
dual port SRAMcomputer graphicscursor
 Summary | Full Text:PDF(729.8KB)

A 300 MHz Dual Port Palette RAM Using Port Swap Architecture
Yasunobu NAKASE Koichiro MASHIKO Yoshio MATSUDA Takeshi TOKUDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9  pp. 1484-1490
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
dual port SRAMgraphicscolor palettesmall cell size
 Summary | Full Text:PDF(729.6KB)

Shared Multibuffer ATM Switches with Hierarchical Queueing and Multicast Functions
Hideaki YAMANAKA Hirotaka SAITO Hirotoshi YAMADA Harufusa KONDOH Hiromi NOTANI Yoshio MATSUDA Kazuyoshi OSHIMA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1996/08/25
Vol. E79-B  No. 8  pp. 1109-1120
Type of Manuscript:  PAPER
Category: Switching and Communication Processing
Keyword: 
ATM switch architecturehierarchical queueingmulticast functionsATM access systemsATM loop systems
 Summary | Full Text:PDF(1.3MB)

A 1.5-V 250-MHz to 3.0-V 622-MHz Operation CMOS Phase-Locked Loop with Precharge Type Phase-Frequency Detector
Harufusa KONDOH Hiromi NOTANI Tsutomu YOSHIMURA Hiroshi SHIBATA Yoshio MATSUDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/04/25
Vol. E78-C  No. 4  pp. 381-388
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits)
Category: Digital Circuits
Keyword: 
PLLPFDVCOCMOSATM
 Summary | Full Text:PDF(672.1KB)

An Efficient Self-Timed Queue Architecture for ATM Switch LSIs
Harufusa KONDOH Hideaki YAMANAKA Masahiko ISHIWAKI Yoshio MATSUDA Masao NAKAYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/12/25
Vol. E77-C  No. 12  pp. 1865-1872
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs)
Category: Multimedia System LSIs
Keyword: 
ATMATM switchLSIself-timed systems
 Summary | Full Text:PDF(760.2KB)

A Line-Mode Test with Data Register for ULSI Memory Architecture
Tsukasa OOISHI Masaki TSUKUDE Kazutani ARIMOTO Yoshio MATSUDA Kazuyasu FUJISHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/11/25
Vol. E76-C  No. 11  pp. 1595-1603
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: DRAM
Keyword: 
line-mode testdata inversion registermain-sub I/O line architecture
 Summary | Full Text:PDF(858KB)

A Shared Multibuffer Architecture for High-Speed ATM Switch LSIs
Harufusa KONDOH Hiromi NOTANI Hideaki YAMANAKA Keiichi HIGASHITANI Hirotaka SAITO Isamu HAYASHI Yoshio MATSUDA Kazuyoshi OSHIMA Masao NAKAYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/25
Vol. E76-C  No. 7  pp. 1094-1101
Type of Manuscript:  Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Improved Binary Digital Architectures
Keyword: 
B-ISDNATMswitchLSIBiCMOS
 Summary | Full Text:PDF(854.7KB)

A Divided/Pausing Bitline Sensing Scheme (DIPS) for ULSI DRAM Core
Hideto HIDAKA Yoshio MATSUDA Kazuyasu FUJISHIMA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/11/25
Vol. E73-E  No. 11  pp. 1852-1854
Type of Manuscript:  Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE)
Category: Integrated Circuits
Keyword: 
 Summary | Full Text:PDF(158.2KB)

Mechanism of Bit Line Mode Soft Error for DRAM
Mikio ASAKURA Yoshio MATSUDA Katsuhiro TSUKAMOTO Kazuyasu FUJISHIMA Tsutomu YOSHIHARA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1987/11/25
Vol. E70-E  No. 11  pp. 1060-1061
Type of Manuscript:  Special Section LETTER (Special Issue: Papers from 1987 National Conference on Semicondutor Devices and Materials IEICE)
Category: Semiconductor Devices
Keyword: 
 Summary | Full Text:PDF(154.8KB)