| Yoshio MATSUDA
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A Divided/Pausing Bitline Sensing Scheme (DIPS) for ULSI DRAM Core Hideto HIDAKA Yoshio MATSUDA Kazuyasu FUJISHIMA | Publication: IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/11/25
Vol. E73-E
No. 11
pp. 1852-1854
Type of Manuscript:
Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE) Category: Integrated Circuits Keyword:
| | Summary | Full Text:PDF | |
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Mechanism of Bit Line Mode Soft Error for DRAM Mikio ASAKURA Yoshio MATSUDA Katsuhiro TSUKAMOTO Kazuyasu FUJISHIMA Tsutomu YOSHIHARA | Publication: IEICE TRANSACTIONS (1976-1990)
Publication Date: 1987/11/25
Vol. E70-E
No. 11
pp. 1060-1061
Type of Manuscript:
Special Section LETTER (Special Issue: Papers from 1987 National Conference on Semicondutor Devices and Materials IEICE) Category: Semiconductor Devices Keyword:
| | Summary | Full Text:PDF | |
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