IEICE Trans

Yoshinori TAKEUCHI

Phase Locking Value Calculator Based on Hardware-Oriented Mathematical Expression Tomoki SUGIURA Jaehoon YU Yoshinori TAKEUCHI
Publication: Publication Date: 2018/12/01 Vol. E101-A No. 12 pp. 2254-2261 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: biomedical engineering, electrocorticography, phase locking value, mean phase coherence, digital signal processing,
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Decomposed Vector Histograms of Oriented Gradients for Efficient Hardware Implementation Koichi MITSUNARI Yoshinori TAKEUCHI Masaharu IMAI Jaehoon YU
Publication: Publication Date: 2018/11/01 Vol. E101-A No. 11 pp. 1766-1775 Type of Manuscript: Special Section PAPER (Special Section on Smart Multimedia & Communication Systems) Category: Vision Keyword: object detection, histograms of oriented gradients, vector decomposition, hardware implementation,
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Deformable Part Model Based Arrhythmia Detection Using Time Domain Features Yuuka HIRAO Yoshinori TAKEUCHI Masaharu IMAI Jaehoon YU
Publication: Publication Date: 2017/11/01 Vol. E100-A No. 11 pp. 2221-2229 Type of Manuscript: Special Section PAPER (Special Section on Smart Multimedia & Communication Systems) Category: Digital Signal Processing Keyword: arrhythmia detection, electrocardiogram, deformable part model, time domain features,
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Incorporating Contextual Information into Bag-of-Visual-Words Framework for Effective Object Categorization Shuang BAI Tetsuya MATSUMOTO Yoshinori TAKEUCHI Hiroaki KUDO Noboru OHNISHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/12/01 Vol. E95-D No. 12 pp. 3060-3068 Type of Manuscript: PAPER Category: Image Recognition, Computer Vision Keyword: object categorization, bag of visual words, contextual information, hierarchical codebook,
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Segmentation of Depth-of-Field Images Based on the Response of ICA Filters Andre CAVALCANTE Allan Kardec BARROS Yoshinori TAKEUCHI Noboru OHNISHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/04/01 Vol. E95-D No. 4 pp. 1170-1173 Type of Manuscript: LETTER Category: Image Recognition, Computer Vision Keyword: image segmentation, depth-of-field, kurtosis,
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A Small-Area and Low-Power SoC for Less-Invasive Pressure Sensing Capsules in Ambulatory Urodynamic Monitoring Hirofumi IWATO Keishi SAKANUSHI Yoshinori TAKEUCHI Masaharu IMAI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 pp. 487-494 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: pressure sensing, urinary bladder, SoC, low power, ASIP,
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Incorporating Top-Down Guidance for Extracting Informative Patches for Image Classification Shuang BAI Tetsuya MATSUMOTO Yoshinori TAKEUCHI Hiroaki KUDO Noboru OHNISHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/03/01 Vol. E95-D No. 3 pp. 880-883 Type of Manuscript: LETTER Category: Pattern Recognition Keyword: patch sampling, informative regions, image classification,
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Two-Stage Configurable Decoder Model for Domain Specific FEC Decoder Design Ittetsu TANIGUCHI Ayataka KOBAYASHI Keishi SAKANUSHI Yoshinori TAKEUCHI Masaharu IMAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 pp. 2659-2668 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: forward error correction (FEC), decoder model,
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Multi-Objective Genetic Programming with Redundancy-Regulations for Automatic Construction of Image Feature Extractors Ukrit WATCHAREERUETAI Tetsuya MATSUMOTO Yoshinori TAKEUCHI Hiroaki KUDO Noboru OHNISHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/09/01 Vol. E93-D No. 9 pp. 2614-2625 Type of Manuscript: PAPER Category: Biocybernetics, Neurocomputing Keyword: multi-objective optimization, genetic programming, redundancy regulation, image feature extraction, non-dominated sorting,
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Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor Takuji HIEDA Hiroaki TANAKA Keishi SAKANUSHI Yoshinori TAKEUCHI Masaharu IMAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3258-3267 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Embedded, Real-Time and Reconfigurable Systems Keyword: partial forwarding, instruction scheduling, compiler, design space exploration,
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Acceleration of Genetic Programming by Hierarchical Structure Learning: A Case Study on Image Recognition Program Synthesis Ukrit WATCHAREERUETAI Tetsuya MATSUMOTO Noboru OHNISHI Hiroaki KUDO Yoshinori TAKEUCHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/10/01 Vol. E92-D No. 10 pp. 2094-2102 Type of Manuscript: PAPER Category: Artificial Intelligence and Cognitive Science Keyword: hierarchical structure genetic programming, acceleration, learning node, training subsets, population integration,
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Optimal Scheme for Search State Space and Scheduling on Multiprocessor Systems Hassan A. YOUNESS Keishi SAKANUSHI Yoshinori TAKEUCHI Ashraf SALEM Abdel-Moneim WAHDAN Masaharu IMAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/04/01 Vol. E92-A No. 4 pp. 1088-1095 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa) Category: Keyword: optimal scheduling, task graphs, state-space search, A^*, geometric analysis,
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Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors Ittetsu TANIGUCHI Praveen RAGHAVAN Murali JAYAPALA Francky CATTHOOR Yoshinori TAKEUCHI Masaharu IMAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/04/01 Vol. E92-A No. 4 pp. 1161-1173 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: address generation unit (AGU), reconfigurable architecture, ASIP design, architecture exploration,
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Heart Instantaneous Frequency Based Estimation of HRV from Blood Pressure Waveforms Fausto LUCENA Allan Kardec BARROS Yoshinori TAKEUCHI Noboru OHNISHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/03/01 Vol. E92-D No. 3 pp. 529-537 Type of Manuscript: PAPER Category: Biological Engineering Keyword: blood pressure (BP), electrocardiogram (ECG), heart rate variability (HRV), heart instantaneous frequency (HIF),
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Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram Hiroaki TANAKA Yoshinori TAKEUCHI Keishi SAKANUSHI Masaharu IMAI Hiroki TAGAWA Yutaka OTA Nobu MATSUMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-A No. 12 pp. 2800-2809 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: System Level Design Keyword: compiler, SIMD instructions, multi-valued decision diagram,
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Gauss-Newton Particle Filter Hui CAO Noboru OHNISHI Yoshinori TAKEUCHI Tetsuya MATSUMOTO Hiroaki KUDO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/06/01 Vol. E90-A No. 6 pp. 1235-1239 Type of Manuscript: LETTER Category: Systems and Control Keyword: particle filter, better proposal distribution, extended Kalman filter, unscented Kalman filter, Gauss-Newton method,
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A Compiler Generation Method for HW/SW Codesign Based on Configurable Processors Shinsuke KOBAYASHI Kentaro MITA Yoshinori TAKEUCHI Masaharu IMAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 pp. 2586-2595 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Hardware/Software Codesign Keyword: compiler generation, ASIP, design space exploration,
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Code Efficiency Evaluation for Embedded Processors Morgan Hirosuke MIKI Mamoru SAKAMOTO Shingo MIYAMOTO Yoshinori TAKEUCHI Toyohiko YOSHIDA Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/04/01 Vol. E85-A No. 4 pp. 811-818 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: code efficiency, profiling, processor architecture,
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Optical Encoding and Decoding of Femtosecond Pulses in the Spectral Domain Using Optical Coupler with Fiber Gratings Shin-ichi WAKABAYASHI Hitomi MORIYA Asako BABA Yoshinori TAKEUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/01/01 Vol. E85-C No. 1 pp. 135-140 Type of Manuscript: Special Section PAPER (Special Issue on Ultrafast Optical Signal Processing and Its Application) Category: OTDM Transmission System, Optical Regeneration and Coding Keyword: fiber grating, femtosecond pulse, spectral separation, directional coupler, optical encoding,
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Proposal of a Multi-Threaded Processor Architecture for Embedded Systems and Its Evaluation Shinsuke KOBAYASHI Yoshinori TAKEUCHI Akira KITAJIMA Masaharu IMAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/03/01 Vol. E84-A No. 3 pp. 748-754 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 13th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: multi-threading, very long instruction word (VLIW), instruction level parallelism, thread level parallelism, HW/SW co-design,
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Separation of Narrow Bandwidth Spectral Light from Femtosecond Pulses Using Optical Coupler with Fiber Grating Asako BABA Hitomi MORIYA Shin-ichi WAKABAYASHI Yukio TOYODA Yoshinori TAKEUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/06/25 Vol. E83-C No. 6 pp. 824-829 Type of Manuscript: Special Section PAPER (Special Issue on Advanced Optical Devices for Next Generation High-Speed Communication Systems and Photonic Networks) Category: Fibers Keyword: fiber grating, femto-second pulse, spectral separation, directional coupler,
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VLSI Architecture for Real-Time Fractal Image Coding Processors Hideki YAMAUCHI Yoshinori TAKEUCHI Masaharu IMAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/03/25 Vol. E83-A No. 3 pp. 452-458 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 12th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: VLSI architecture, image coding, fractal compression,
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Synthesizable HDL Generation for Pipelined Processors from a Micro-Operation Description Makiko ITOH Yoshinori TAKEUCHI Masaharu IMAI Akichika SHIOMI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/03/25 Vol. E83-A No. 3 pp. 394-400 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 12th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: pipelined processor, micro-operation description, HDL generation, instruction set processor,
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A Performance Optimization Method for Pipelined ASIPs in Consideration of Clock Frequency Katsuya SHINOHARA Norimasa OHTSUKI Yoshinori TAKEUCHI Masaharu IMAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/11/25 Vol. E82-A No. 11 pp. 2356-2365 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: performance optimization, clock frequency tuning, pipelined ASIPs, HW/SW co-design,
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An Optimization Algorithm for High Performance ASIP Design with Considering the RAM and ROM Sizes Nguyen Ngoc BINH Masaharu IMAI Yoshinori TAKEUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/12/25 Vol. E81-A No. 12 pp. 2612-2620 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Co-design Keyword: ASIP, HW/SW partitioning, performance estimation, RAM, ROM,
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Effectiveness of a High Speed Context Switching Method Using Register Bank Jun-ichi ITO Takumi NAKANO Yoshinori TAKEUCHI Masaharu IMAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/12/25 Vol. E81-A No. 12 pp. 2661-2667 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: LSI Architecture Keyword: hard real-time system, real-time OS, context switching, register bank, context switching module (CSM), hardware OS,
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Distributed Load Balancing Schemes for Parallel Video Encoding System Zhaochen HUANG Yoshinori TAKEUCHI Hiroaki KUNIEDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/05/25 Vol. E77-A No. 5 pp. 923-930 Type of Manuscript: PAPER Category: Parallel/Multidimensional Signal Processing Keyword: distributed load balancing, convergence, video encoding, parallel processing,
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RHINE: Reconfigurable Multiprocessor System for Video CODEC Yoshinori TAKEUCHI Zhao-Chen HUANG Masatomo SAEKI Hiroaki KUNIEDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/06/25 Vol. E76-A No. 6 pp. 947-956 Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 1992 Joint Technical Conference on Circuits/Systems,Computers and Communications (JTC-CSCC'92)) Category: Methods and Circuits for Signal Processing Keyword: parallel processing, load balancing, video CODEC, parallel architecture, reconfigurable architecture,
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Space Partitioning Image Processing Technique for Parallel Recursive Half Toning Yoshinori TAKEUCHI Hiroaki KUNIEDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/04/25 Vol. E76-A No. 4 pp. 603-612 Type of Manuscript: PAPER Category: Digital Signal Processing Keyword: parallel processing, recursive filtering, digital half tone, parallel algorithm, space partitioning processing,
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Parallel Processing Architecture Design for Two-Dimensional Image Processing Using Spatial Expansion of the Signal Flow Graph Tsuyoshi ISSHIKI Yoshinori TAKEUCHI Hiroaki KUNIEDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/03/25 Vol. E76-A No. 3 pp. 337-348 Type of Manuscript: Special Section PAPER (Special Section on the 5th Karuizawa Workshop on Circuits and Systems) Category: Keyword: architecture design, spatial expansion of SFG, pixel SFG, frame SFG,
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Two Dimensional Space Partition Recursive Filtering Algorithm on Rectangular Processor Array Yoshinori TAKEUCHI Hiroaki KUNIEDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1991/01/25 Vol. E74-A No. 1 pp. 42-48 Type of Manuscript: PAPER Category: Digital Signal Processing Keyword:
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