Yoshinori KATSURA


A Floorplanning Method with Topological Constraint Manipulation in VLSI Building Block Layout
Tetsushi KOIDE Yoshinori KATSURA Katsumi YAMATANI Shin'ichi WAKABAYASHI Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12  pp. 2053-2057
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
building block layoutfloorplanningrelative placementtopological constraintstrong respecttentative insertionblock reshaping
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