Yoshinori GOTOH

A New High-Density 10T CMOS Gate-Array Base Cell for Two-Port SRAM Applications
Nobutaro SHIBATA Yoshinori GOTOH Takako ISHIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/06/01
Vol. E99-C  No. 6  pp. 717-726
Type of Manuscript:  PAPER
Category: Integrated Electronics
10T typebitline capacitanceCMOSgate arrayhigh speedlow powermemory-oriented base cellshared contacttwo-port SRAM
 Summary | Full Text:PDF(1.7MB)

High-Performance Memory Macrocells with Row and Column Sliceable Architecture
Nobutaro SHIBATA Yoshinori GOTOH Shigeru DATE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/11/25
Vol. E76-C  No. 11  pp. 1641-1648
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: Application Specific Memory
ASICCMOSmacrocellmemoryconfigurablerow sliceabledecodershort design Turn-Around-Time (TAT)
 Summary | Full Text:PDF(692.2KB)