Yoshinobu YAMAGAMI


A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses
Hiroyuki YAMAUCHI Toshikazu SUZUKI Yoshinobu YAMAGAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4  pp. 749-757
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Memory
Keyword: 
SRAM1R/1W-SRAMdisturbed accessSNMwrite margincell current
 Summary | Full Text:PDF

A Differential Cell Terminal Biasing Scheme Enabling a Stable Write Operation against a Large Random Threshold Voltage (Vth) Variation
Hiroyuki YAMAUCHI Toshikazu SUZUKI Yoshinobu YAMAGAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1526-1534
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
SRAMcell terminal biasingdifferential cell terminalSNMwrite margindisturb
 Summary | Full Text:PDF

0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier
Toshikazu SUZUKI Yoshinobu YAMAGAMI Ichiro HATANAKA Akinori SHIBAYAMA Hironori AKAMATSU Hiroyuki YAMAUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 630-638
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Memory
Keyword: 
SRAMlow-voltagewide-voltageSoC
 Summary | Full Text:PDF