IEICE Trans

Yoshinobu HIGAMI

Formulation of a Test Pattern Measure That Counts Distinguished Fault-Pairs for Circuit Fault Diagnosis Tsutomu INAMOTO Yoshinobu HIGAMI
Publication: Publication Date: 2020/12/01 Vol. E103-A No. 12 pp. 1456-1463 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: LSI testing, circuit fault diagnosis, set cover problem, greedy heuristic, fault-pair,
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FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST Hanan T. Al-AWADHI Tomoki AONO Senling WANG Yoshinobu HIGAMI Hiroshi TAKAHASHI Hiroyuki IWATA Yoichi MAEDA Jun MATSUSHIMA
Publication: Publication Date: 2020/11/01 Vol. E103-D No. 11 pp. 2289-2301 Type of Manuscript: PAPER Category: Dependable Computing Keyword: POST, BIST, Multi-Cycle Test, Fault detection degradation, FF-Control Point Insertion technique, FF selection,
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Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines Hiroyuki YOTSUYANAGI Kotaro ISE Masaki HASHIZUME Yoshinobu HIGAMI Hiroshi TAKAHASHI
Publication: Publication Date: 2017/12/01 Vol. E100-A No. 12 pp. 2842-2850 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: resistive open, small delay fault, adjacent line, delay variation, anomaly detection,
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A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line Yoshinobu HIGAMI Senling WANG Hiroshi TAKAHASHI Shin-ya KOBAYASHI Kewal K. SALUJA
Publication: Publication Date: 2017/09/01 Vol. E100-D No. 9 pp. 2224-2227 Type of Manuscript: LETTER Category: Dependable Computing Keyword: fault diagnosis, bridging faults, clock lines,
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Trip-Based Integer Linear Programming Model for Static Multi-Car Elevator Operation Problems Tsutomu INAMOTO Yoshinobu HIGAMI Shin-ya KOBAYASHI
Publication: Publication Date: 2017/02/01 Vol. E100-A No. 2 pp. 385-394 Type of Manuscript: Special Section PAPER (Special Section on Mathematical Systems Science and its Applications) Category: Keyword: elevator operation problem, multi-car elevator system, integer linear programming, interference prevention,
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Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment Yoshinobu HIGAMI Hiroshi TAKAHASHI Shin-ya KOBAYASHI Kewal K. SALUJA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/06/01 Vol. E96-D No. 6 pp. 1323-1331 Type of Manuscript: PAPER Category: Dependable Computing Keyword: test generation, fault simulation, clock line, delay fault,
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Generation of Diagnostic Tests for Transition Faults Using a Stuck-At ATPG Tool Yoshinobu HIGAMI Satoshi OHNO Hironori YAMAOKA Hiroshi TAKAHASHI Yoshihiro SHIMIZU Takashi AIKYO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/04/01 Vol. E95-D No. 4 pp. 1093-1100 Type of Manuscript: PAPER Category: Dependable Computing Keyword: fault diagnosis, test generation, transition faults, stuck-at ATPG,
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Addressing Defect Coverage through Generating Test Vectors for Transistor Defects Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3128-3135 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verfication Keyword: test generation, transistor defects, stuck-at tests, defect coverage,
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Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3506-3513 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: fault simulation, test generation, stuck-open faults, stuck-at tests, defect coverage,
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Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information Yuzo TAKAMATSU Hiroshi TAKAHASHI Yoshinobu HIGAMI Takashi AIKYO Koji YAMAZAKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 675-682 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: Fault Diagnosis Keyword: diagnosis, fault model, fault location, fault simulation, combinational circuits, pass/fail information,
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Post-BIST Fault Diagnosis for Multiple Faults Hiroshi TAKAHASHI Yoshinobu HIGAMI Shuhei KADOYAMA Yuzo TAKAMATSU Koji YAMAZAKI Takashi AIKYO Yasuo SATO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 771-775 Type of Manuscript: Special Section LETTER (Special Section on Test and Verification of VLSIs) Category: Keyword: post-BIST fault diagnosis, multiple stuck-at faults, combinational circuits, pass/fail information,
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Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 690-699 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: Defect-Based Testing Keyword: transistor short, fault simulation, test generation, stuck-at test tool,
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On Finding Don't Cares in Test Sequences for Sequential Circuits Yoshinobu HIGAMI Seiji KAJIHARA Irith POMERANZ Shin-ya KOBAYASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/11/01 Vol. E89-D No. 11 pp. 2748-2755 Type of Manuscript: PAPER Category: Dependable Computing Keyword: test generation, don't care value, sequential circuit, stuck-at fault,
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Generation of Test Sequences with Low Power Dissipation for Sequential Circuits Yoshinobu HIGAMI Shin-ya KOBAYASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/03/01 Vol. E87-D No. 3 pp. 530-536 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSI) Category: Test Generation and Compaction Keyword: LSI testing, sequential circuit, test generation, low power dissipation, stuck-at fault,
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Diagnosing Crosstalk Faults in Sequential Circuits Using Fault Simulation Hiroshi TAKAHASHI Marong PHADOONGSIDHI Yoshinobu HIGAMI Kewal K. SALUJA Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/10/01 Vol. E85-D No. 10 pp. 1515-1525 Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI) Category: Test and Diagnosis for Timing Faults Keyword: diagnosis, crosstalk fault, fault simulation, sequential circuit,
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Test Generation for Sequential Circuits under IDDQ Testing Toshiyuki MAEDA Yoshinobu HIGAMI Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/07/25 Vol. E81-D No. 7 pp. 689-696 Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI) Category: IDDQ Testing Keyword: sequential circuit, test generation, IDDQ testing, bridging fault,
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A Reduced Scan Shift Method for Sequential Circuit Testing Yoshinobu HIGAMI Seiji KAJIHARA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/12/25 Vol. E77-A No. 12 pp. 2010-2016 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: sequential circuit, test generation, design for testability, scan circuit, reduced scan shift,
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Test Sequence Generation for Sequential Circuits with Distinguishing Sequences Yoshinobu HIGAMI Seiji KAJIHARA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/10/25 Vol. E76-A No. 10 pp. 1730-1737 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: distinguishing sequence, stuck-at fault, sequential circuit, test sequence generation, design rechnique,
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