Yoshikazu SAITO


Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs
Chizu MATSUMOTO Yuichi HAMAMURA Michinobu NAKAO Kaname YAMASAKI Yoshikazu SAITO Shun'ichi KANEKO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/01/01
Vol. E96-C  No. 1  pp. 108-114
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
random access memorysystem-on-chipredundancyfuse
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