Yoshikazu MOROOKA


A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test
Masaru HARAGUCHI Tokuya OSAWA Akira YAMAZAKI Chikayoshi MORISHIMA Toshinori MORIHARA Yoshikazu MOROOKA Yoshihiro OKUNO Kazutami ARIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Vol. E92-C  No. 4  pp. 453-459
Type of Manuscript:  Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
Category: 
Keyword: 
DDR interfaceSoCround-trip-timeloop-backed test
 Summary | Full Text:PDF

An Embedded DRAM Hybrid Macro with Auto Signal Management and Enhanced-on-Chip Tester
Naoya WATANABE Fukashi MORISHITA Yasuhiko TAITO Akira YAMAZAKI Tetsushi TANIZAKI Katsumi DOSAKA Yoshikazu MOROOKA Futoshi IGAUE Katsuya FURUE Yoshihiro NAGURA Tatsunori KOMOIKE Toshinori MORIHARA Atsushi HACHISUKA Kazutami ARIMOTO Hideyuki OZAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4  pp. 624-634
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Design Methods and Implementation
Keyword: 
embedded DRAMvarious DRAM macroslow voltage operationshort TATBIST
 Summary | Full Text:PDF

A 0.18 µm 32 Mb Embedded DRAM Macro for 3-D Graphics Controller
Akira YAMAZAKI Takeshi FUJINO Kazunari INOUE Isamu HAYASHI Hideyuki NODA Naoya WATANABE Fukashi MORISHITA Katsumi DOSAKA Yoshikazu MOROOKA Shinya SOEDA Kazutami ARIMOTO Setsuo WAKE Kazuyasu FUJISHIMA Hideyuki OZAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/09/01
Vol. E85-C  No. 9  pp. 1697-1708
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
embedded DRAMsystem on chip3-D graphics concurrent operation
 Summary | Full Text:PDF

A Low Power and High Speed Data Transfer Scheme with Asynchronous Compressed Pulse Width Modulation for AS-Memory
Tadaaki YAMAUCHI Yoshikazu MOROOKA Hideyuki OZAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/07/25
Vol. E79-C  No. 7  pp. 934-941
Type of Manuscript:  Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996))
Category: Interface Circuits
Keyword: 
 Summary | Full Text:PDF

Cell-Plate-Line/Bit-Line Complementary Sensing (CBCS) Architecture for Ultra Low-Power DRAM's
Takeshi HAMAMOTO Yoshikazu MOROOKA Mikio ASAKURA Hideyuki OZAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/07/25
Vol. E79-C  No. 7  pp. 1003-1012
Type of Manuscript:  Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996))
Category: Memory
Keyword: 
 Summary | Full Text:PDF

Fully Self-Timing Data-Bus Architecture for 64-Mb DRAMs
Tadaaki YAMAUCHI Koji TANAKA Kiyohiro FURUTANI Yoshikazu MOROOKA Hiroshi MIYAMOTO Hideyuki OZAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7  pp. 858-865
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
self-timing data-bustiming delaydevice fluctuationamplifier64-Mb DRAMs
 Summary | Full Text:PDF

An Efficient Back-Bias Generator with Hybrid Pumping Circuit for 1.5-V DRAM's
Yasuhiko TSUKIKAWA Takeshi KAJIMOTO Yasuhiko OKASAKA Yoshikazu MOROOKA Kiyohiro FURUTANI Hiroshi MIYAMOTO Hideyuki OZAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/05/25
Vol. E77-C  No. 5  pp. 864-868
Type of Manuscript:  Special Section LETTER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
Category: 
Keyword: 
 Summary | Full Text:PDF