IEICE Trans

Yoshikazu KIYOSHIGE

A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core Osamu NISHII Yoichi YUYAMA Masayuki ITO Yoshikazu KIYOSHIGE Yusuke NITTA Makoto ISHIKAWA Tetsuya YAMADA Junichi MIYAKOSHI Yasutaka WADA Keiji KIMURA Hironori KASAHARA Hideo MAEJIMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 pp. 663-669 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: heterogeneous, instruction set, MMU,
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An Embedded Processor Core for Consumer Appliances with 2.8GFLOPS and 36 M Polygons/s FPU Fumio ARAKAWA Motokazu OZAWA Osamu NISHII Toshihiro HATTORI Takeshi YOSHINAGA Tomoichi HAYASHI Yoshikazu KIYOSHIGE Takashi OKADA Masakazu NISHIBORI Tomoyuki KODAMA Tatsuya KAMEI Makoto ISHIKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3068-3074 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: System Level Design Keyword: embedded processor, architecture, FPU, pipeline,
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Application of High Quality Built-in Test Using Neighborhood Pattern Generator to Industrial Designs Kazumi HATAYAMA Michinobu NAKAO Yoshikazu KIYOSHIGE Koichiro NATSUME Yasuo SATO Takaharu NAGUMO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3318-3323 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Test Keyword: BIST, test pattern generator, neighborhood pattern, LFSR, reseeding,
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High Quality Delay Test Generation Based on Multiple-Threshold Gate-Delay Fault Model Michinobu NAKAO Yoshikazu KIYOSHIGE Yasuo SATO Kazumi HATAYAMA Satoshi FUKUMOTO Kazuhiko IWASAKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/10/01 Vol. E85-D No. 10 pp. 1506-1514 Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI) Category: Test and Diagnosis for Timing Faults Keyword: delay testing, path selection, fault simulation, test generation, path-status graph,
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Deterministic Built-in Test with Neighborhood Pattern Generator Michinobu NAKAO Yoshikazu KIYOSHIGE Koichiro NATSUME Kazumi HATAYAMA Satoshi FUKUMOTO Kazuhiko IWASAKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/05/01 Vol. E85-D No. 5 pp. 874-883 Type of Manuscript: PAPER Category: Fault Tolerance Keyword: BIST, test pattern generator, reseeding, bit-flipping, seed generation,
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