IEICE Trans

Yoshihito AMEMIYA

An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs Yusuke TSUGITA Ken UENO Tetsuya HIROSE Tetsuya ASAI Yoshihito AMEMIYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/06/01 Vol. E93-C No. 6 pp. 835-841 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: digital circuits, threshold voltage variation, compensation circuit, PVT variation,
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High-Resistance Resistor Consisting of a Subthreshold CMOS Differential Pair Shin'ichi ASAI Ken UENO Tetsuya ASAI Yoshihito AMEMIYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/06/01 Vol. E93-C No. 6 pp. 741-746 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: CMOS, integrated circuit, resistor, high resistance, differential circuit, subthreshold,
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Low-Voltage Process-Compensated VCO with On-Chip Process Monitoring and Body-Biasing Circuit Techniques Ken UENO Tetsuya HIROSE Tetsuya ASAI Yoshihito AMEMIYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3079-3081 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: voltage-controlled oscillator, process variation, process compensation, body bias, current reference,
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Stochastic Resonance in an Array of Locally-Coupled McCulloch-Pitts Neurons with Population Heterogeneity Akira UTAGAWA Tohru SAHASHI Tetsuya ASAI Yoshihito AMEMIYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/10/01 Vol. E92-A No. 10 pp. 2508-2513 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications) Category: Nonlinear Problems Keyword: stochastic resonance, image processing, neural networks,
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Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits Taichi OGAWA Tetsuya HIROSE Tetsuya ASAI Yoshihito AMEMIYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/02/01 Vol. E92-A No. 2 pp. 436-442 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: subthreshold, MOS, circuit, threshold logic, majority logic, gate, current mode,
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Noise-Induced Synchronization among Sub-RF CMOS Analog Oscillators for Skew-Free Clock Distribution Akira UTAGAWA Tetsuya ASAI Tetsuya HIROSE Yoshihito AMEMIYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/09/01 Vol. E91-A No. 9 pp. 2475-2481 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications) Category: Electronic Circuits and Systems Keyword: clock distribution, synchronization, nonlinear oscillators, clock skew,
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An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits Akira UTAGAWA Tetsuya ASAI Tetsuya HIROSE Yoshihito AMEMIYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/10/01 Vol. E90-A No. 10 pp. 2108-2115 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications) Category: Neuron and Neural Networks Keyword: neuromorphic analog integrated circuits, pulse density modulation, noise shaping, subthreshold CMOS circuits,
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Single-Electron Logic Systems Based on a Graphical Representation of Digital Functions Yoshihito AMEMIYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 pp. 1504-1511 Type of Manuscript: INVITED PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: single electron circuit, logic gate, binary decision diagram, quantum dot, nanostructure,
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A CMOS Watchdog Sensor for Certifying the Quality of Various Perishables with a Wider Activation Energy Ken UENO Tetsuya HIROSE Tetsuya ASAI Yoshihito AMEMIYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/04/01 Vol. E89-A No. 4 pp. 902-907 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: CMOS, sensor, subthreshold, translinear, low power, quality guarantee,
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Ultralow-Power Current Reference Circuit with Low Temperature Dependence Tetsuya HIROSE Toshimasa MATSUOKA Kenji TANIGUCHI Tetsuya ASAI Yoshihito AMEMIYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/06/01 Vol. E88-C No. 6 pp. 1142-1147 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit and Device Technologies) Category: Building Block Keyword: CMOS, reference, subthreshold, weak inversion, low power, temperature dependence,
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FOREWORD Yoshihito AMEMIYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/11/01 Vol. E87-C No. 11 pp. 1747-1747 Type of Manuscript: FOREWORD Category: Keyword:
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A CMOS Reaction-Diffusion Circuit Based on Cellular-Automaton Processing Emulating the Belousov-Zhabotinsky Reaction Tetsuya ASAI Yuusaku NISHIMIYA Yoshihito AMEMIYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/09/01 Vol. E85-A No. 9 pp. 2093-2096 Type of Manuscript: Special Section LETTER (Special Section on Nonlinear Theory and Its Applications) Category: Keyword: reaction-diffusion system, reaction-diffusion chip, cellular automaton, Belousov-Zhabotinsky reaction,
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Analog Computation Using Coupled-Quantum-Dot Spin Glass Nan-Jian WU Hassu LEE Yoshihito AMEMIYA Hitoshi YASUNAGA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/09/25 Vol. E82-C No. 9 pp. 1623-1629 Type of Manuscript: Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms) Category: Quantum Devices and Circuits Keyword: analog computation, spin glass, quantum dot, spin, combinatorial optimization problem,
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A Multiple-Valued Hopfield Network Device Using Single-Electron Circuits Takashi YAMADA Yoshihito AMEMIYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/09/25 Vol. E82-C No. 9 pp. 1615-1622 Type of Manuscript: Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms) Category: Quantum Devices and Circuits Keyword: single electron, Hopfield network, multiple-valued,
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Multiple-Valued Inverter Using a Single-Electron-Tunneling Circuit Masamichi AKAZAWA Kentarou KANAAMI Takashi YAMADA Yoshihito AMEMIYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/09/25 Vol. E82-C No. 9 pp. 1607-1614 Type of Manuscript: Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms) Category: Quantum Devices and Circuits Keyword: single electron, SET, multiple-valued, Coulomb blockade,
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Photoirradiation Effects in a Single-Electron Tunnel Junction Array Michiharu TABE Yoichi TERAO Noboru ASAHI Yoshihito AMEMIYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/01/25 Vol. E81-C No. 1 pp. 36-41 Type of Manuscript: Special Section PAPER (Special Issue on Technology Challenges for Single Electron Devices) Category: Keyword: SET, photoirradiation, Monte Carlo simulation, photonic devices,
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Single-Electron Logic Systems Based on the Binary Decision Diagram Noboru ASAHI Masamichi AKAZAWA Yoshihito AMEMIYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/01/25 Vol. E81-C No. 1 pp. 49-56 Type of Manuscript: Special Section PAPER (Special Issue on Technology Challenges for Single Electron Devices) Category: Keyword: binary decision diagram, BDD, single electron, logic circuit, adder, comparator,
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Single-Electron Majority Logic Circuits Hiroki IWAMURA Masamichi AKAZAWA Yoshihito AMEMIYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/01/25 Vol. E81-C No. 1 pp. 42-48 Type of Manuscript: Special Section PAPER (Special Issue on Technology Challenges for Single Electron Devices) Category: Keyword: single electron majority logic, threshold logic, gate, circuit, thermal noise,
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Eliciting the Potential Functions of Single-Electron Circuits Masamichi AKAZAWA Yoshihito AMEMIYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/07/25 Vol. E80-C No. 7 pp. 849-858 Type of Manuscript: INVITED PAPER (Special Issue on New Concept Device and Novel Architecture LSIs) Category: Keyword: single-electron, SET, logic, circuit, stability diagram, Boltzmann machine,
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Analog Computation Using Quantum Structures--A Promising Computation Architecture for Quantum Processors-- Yoshihito AMEMIYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/11/25 Vol. E79-C No. 11 pp. 1481-1486 Type of Manuscript: INVITED PAPER (Special Issue on Quantum Effect Devices and Their Fabrication Technologies) Category: Keyword: analog computation, quantum device, processing architecture, optimization problem,
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Very-High-Speed Analog Neural Network LSI Using Super Self-Aligned Si Bipolar Process Technology Shigeki AISAWA Kazuhiro NOGUCHI Masafumi KOGA Takao MATSUMOTO Yoshihito AMEMIYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/06/25 Vol. E77-C No. 6 pp. 1005-1008 Type of Manuscript: LETTER Category: Integrated Electronics Keyword: neural network, analog LSI, optical WDM,
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Deterministic Boltzmann Machine Learning Improved for Analog LSI Implementation Takashi MORIE Yoshihito AMEMIYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/07/25 Vol. E76-C No. 7 pp. 1167-1173 Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs) Category: Neural Networks and Chips Keyword: neural network, Boltzmann machine, analog LSI, mean-field theory learning,
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Analog VLSI Implementation of Adaptive Algorithms by an Extended Hebbian Synapse Circuit Takashi MORIE Osamu FUJITA Yoshihito AMEMIYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/03/25 Vol. E75-C No. 3 pp. 303-311 Type of Manuscript: Special Section PAPER (Special Issue on Analog LSI and Related Technology) Category: Keyword: neural network, backpropagation, Boltzmann machine, analog LSI, synapse, Hebb learning,
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Emitter-Resistance Effect on Cutoff Frequency of Widegap-Emitter Si HBTs Mamoru UGAJIN Yoshihito AMEMIYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1991/06/25 Vol. E74-C No. 6 pp. 1609-1614 Type of Manuscript: Special Section PAPER (Special Issue on Device and Process Simulation for Ultra Large Scale Integration) Category: Keyword:
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