Yong DOU

Efficient Parallel Interference Cancellation MIMO Detector for Software Defined Radio on GPUs
Rongchun LI Yong DOU Jie ZHOU Chen CHEN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/06/01
Vol. E97-A  No. 6  pp. 1388-1395
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
GPU, SDR, MIMO detector, parallel interference cancellation (PIC), 
 Summary | Full Text:PDF(1.5MB)
An Efficient Parallel SOVA-Based Turbo Decoder for Software Defined Radio on GPU
Rongchun LI Yong DOU Jiaqing XU Xin NIU Shice NI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/05/01
Vol. E97-A  No. 5  pp. 1027-1036
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
GPU, CUDA, SDR, Turbo decoder, SOVA, 
 Summary | Full Text:PDF(2.2MB)
Design and Implement of High Performance Crypto Coprocessor
Shice NI Yong DOU Kai CHEN Jie ZHOU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/04/01
Vol. E97-A  No. 4  pp. 989-990
Type of Manuscript:  LETTER
Category: Algorithms and Data Structures
Keyword: 
crypto coprocessor, reconfigurable crypto block, security protocol, accelerator, 
 Summary | Full Text:PDF(422.6KB)
Window Memory Layout Scheme for Alternate Row-Wise/Column-Wise Matrix Access
Lei GUO Yuhua TANG Yong DOU Yuanwu LEI Meng MA Jie ZHOU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/12/01
Vol. E96-D  No. 12  pp. 2765-2775
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
window memory layout scheme (WMLS), alternate row-wise/column-wise matrix access, SDRAM, GPU, FPGA, 
 Summary | Full Text:PDF(1.4MB)
Parallel Sparse Cholesky Factorization on a Heterogeneous Platform
Dan ZOU Yong DOU Rongchun LI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/04/01
Vol. E96-A  No. 4  pp. 833-834
Type of Manuscript:  LETTER
Category: Algorithms and Data Structures
Keyword: 
sparse Cholesky factorization, supernodal method, GPU, 
 Summary | Full Text:PDF(290.5KB)
Design and Implementation of the Parameterized Multi-Standard High-Throughput Radix-4 Viterbi Decoder on FPGA
Rongchun LI Yong DOU Yuanwu LEI Shice NI Song GUO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2012/05/01
Vol. E95-B  No. 5  pp. 1602-1611
Type of Manuscript:  PAPER
Category: Fundamental Theories for Communications
Keyword: 
multi-standard, radix-4, Viterbi decoder, FPGA, 
 Summary | Full Text:PDF(2.4MB)
FPGA-Specific Custom VLIW Architecture for Arbitrary Precision Floating-Point Arithmetic
Yuanwu LEI Yong DOU Jie ZHOU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/11/01
Vol. E94-D  No. 11  pp. 2173-2183
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
variable-precision floating-point (VP) arithmetic, Very Long Instruction Word (VLIW), elementary function, Newton's method, polynomial approximation, FPGA, 
 Summary | Full Text:PDF(2.1MB)