Yoko KAMIDOI


ASAver.1: An FPGA-Based Education Board for Computer Architecture/System Design
Hiroyuki OCHI Yoko KAMIDOI Hideyuki KAWABATA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10  pp. 1826-1833
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
education of computer architecturesystem designDLX-like pipelined RISC processorfield-programmable gate arrayverilog-HDL
 Summary | Full Text:PDF(1020.4KB)

An Efficient Hypergraph Bisection Algorithm for Partitioning VLSI Circuits
Yoko KAMIDOI Shin'ichi WAKABAYASHI Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10  pp. 1272-1279
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
hypergraphbisectionnetgraphcircuit partitioning
 Summary | Full Text:PDF(699.9KB)