Yoji NISHIO

A 167-MHz 1-Mbit CMOS Synchronous Cache SRAM
Hideharu YAHATA Yoji NISHIO Kunihiro KOMIYAJI Hiroshi TOYOSHIMA Atsushi HIRAISHI Yoshitaka KINOSHITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/04/25
Vol. E80-C  No. 4  pp. 557-565
Type of Manuscript:  Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
Category: 
Keyword: 
CMOS, high speed, cache SRAM, chip floor plan, sense amplifier, output register, setup/hold time, 
 Summary | Full Text:PDF
Design of the Basic Cell and Metallized RAM for 0.5 µm CMOS Gate Array
Yoji NISHIO Hideo HARA Masahiro IWAMURA Yasuo KAMINAGA Katsunori KOIKE Kosaku HIROSE Takayuki NOTO Satoshi OGUCHI Yoshihiko YAMAMOTO Takeshi ONO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/09/25
Vol. E78-C  No. 9  pp. 1255-1262
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
gate array, basic cell, compiled RAM, metallized RAM, 
 Summary | Full Text:PDF
Design Considerations for Low-Voltage Crystal Oscillator Circuit in a 1.8-V Single Chip Microprocessor
Shigeo KUBOKI Takehiro OHTA Junichi KONO Yoji NISHIO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/05/25
Vol. E76-C  No. 5  pp. 701-707
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and Low-Voltage Integrated Circuits)
Category: 
Keyword: 
crystal oscillator, CMOS oscillation circuit, open loop-gain, microprocessor, low voltage oscillator, 
 Summary | Full Text:PDF
A Master Chip Design of 0.5 µm Mixed BiCMOS/CMOS Channelless Gate Array Family
Yoji NISHIO Noriaki OKA Shigeru TAKAHASHI Manabu SHIBATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1991/11/25
Vol. E74-C  No. 11  pp. 3749-3756
Type of Manuscript:  Special Section PAPER (Special Issue on the High Performance ASIC and Microprocessor)
Category: Circuit Design
Keyword: 
 Summary | Full Text:PDF