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A Master Chip Design of 0.5 µm Mixed BiCMOS/CMOS Channelless Gate Array Family Yoji NISHIO Noriaki OKA Shigeru TAKAHASHI Manabu SHIBATA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1991/11/25
Vol. E74-C
No. 11
pp. 3749-3756
Type of Manuscript:
Special Section PAPER (Special Issue on the High Performance ASIC and Microprocessor) Category: Circuit Design Keyword:
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