Yinhe HAN


A New Multiple-Round Dimension-Order Routing for Networks-on-Chip
Binzhang FU Yinhe HAN Huawei LI Xiaowei LI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/04/01
Vol. E94-D  No. 4  pp. 809-821
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
network-on-chip (NoC)fault-tolerant routingmultiple round dimension-order routingturn model
 Summary | Full Text:PDF(1.1MB)

Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power
Jun LIU Yinhe HAN Xiaowei LI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8  pp. 2223-2232
Type of Manuscript:  PAPER
Category: Information Network
Keyword: 
selective encodingtest data compressiontest power reductionflexible groupingX-filling
 Summary | Full Text:PDF(565.6KB)

A Novel Post-Silicon Debug Mechanism Based on Suspect Window
Jianliang GAO Yinhe HAN Xiaowei LI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/05/01
Vol. E93-D  No. 5  pp. 1175-1185
Type of Manuscript:  PAPER
Category: Information Network
Keyword: 
debugscan dumpreal-time tracesuspect window
 Summary | Full Text:PDF(1.1MB)

BAT: Performance-Driven Crosstalk Mitigation Based on Bus-Grouping Asynchronous Transmission
Guihai YAN Yinhe HAN Xiaowei LI Hui LIU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/10/01
Vol. E91-C  No. 10  pp. 1690-1697
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
crosstalk delayon-chip busesbus-grouping transmissionasynchronousshielding
 Summary | Full Text:PDF(803KB)

Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time
Yu HU Yinhe HAN Xiaowei LI Huawei LI Xiaoqing WEN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/10/01
Vol. E89-D  No. 10  pp. 2616-2625
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
compressionrun-length codingrandom access scanpower dissipationtest application time
 Summary | Full Text:PDF(380.6KB)

Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores
Yinhe HAN Yu HU Xiaowei LI Huawei LI Anshuman CHANDRA Xiaoqing WEN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/09/01
Vol. E88-D  No. 9  pp. 2126-2134
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
SOC testingwrapper designscan slicesoverlapping
 Summary | Full Text:PDF(652.3KB)