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Yen-Ting LIN
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay
Juinn-Dar HUANG
Chia-I CHEN
Wan-Ling HSU
Yen-Ting LIN
Jing-Yang JOU
Publication:
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date:
2012/02/01
Vol.
E95-A
No.
2
pp.
559-566
Type of Manuscript:
PAPER
Category:
VLSI Design Technology and CAD
Keyword:
Behavioral synthesis
,
distributed register-file
,
performance optimization
,
low-power
,
resource binding
,
scheduling
,
Summary
|
Full Text:PDF
Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture
Juinn-Dar HUANG
Chia-I CHEN
Yen-Ting LIN
Wan-Ling HSU
Publication:
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date:
2011/04/01
Vol.
E94-A
No.
4
pp.
1151-1155
Type of Manuscript:
LETTER
Category:
VLSI Design Technology and CAD
Keyword:
communication synthesis
,
distributed register-file microarchitecture
,
interconnect minimization
,
resource binding
,
scheduling
,
Summary
|
Full Text:PDF