Yasuyuki MIURA


The Performance Evaluation of a 3D Torus Network Using Partial Link-Sharing Method in NoC Router Buffer
Naohisa FUKASE Yasuyuki MIURA Shigeyoshi WATANABE M.M. HAFIZUR RAHMAN 
Publication:   
Publication Date: 2017/10/01
Vol. E100-D  No. 10  pp. 2478-2492
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
interconnection networknetwork-on-chip (NoC)routermulti-port memory
 Summary | Full Text:PDF(4.8MB)

Reconfigurable Dynamic Logic Circuit Generating t-Term Boolean Functions Based on Double-Gate CNTFETs
Manabu KOBAYASHI Hiroshi NINOMIYA Yasuyuki MIURA Shigeyoshi WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/05/01
Vol. E97-A  No. 5  pp. 1051-1058
Type of Manuscript:  PAPER
Category: Circuit Theory
Keyword: 
reconfigurable logic circuitambipolar double-gate devicesdynamic logicCNTFETs
 Summary | Full Text:PDF(817.2KB)

Reconfigurable Circuit Design Based on Arithmetic Logic Unit Using Double-Gate CNTFETs
Hiroshi NINOMIYA Manabu KOBAYASHI Yasuyuki MIURA Shigeyoshi WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/02/01
Vol. E97-A  No. 2  pp. 675-678
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
reconfigurable logic circuit designambipolar devicedouble-gate CNTFETbinary decision diagramarithmetic logic unit
 Summary | Full Text:PDF(479.7KB)