Yasutaka WADA


Efficient and Precise Profiling, Modeling and Management on Power and Performance for Power Constrained HPC Systems
Yuan HE Yasutaka WADA Wenchao LUO Ryuichi SAKAMOTO Guanqin PAN Thang CAO Masaaki KONDO 
Publication:   
Publication Date: 2021/06/01
Vol. E104-C  No. 6  pp. 237-246
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
HPCperformancepowerprofilingmodelingcapping
 Summary | Full Text:PDF(1MB)

A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core
Osamu NISHII Yoichi YUYAMA Masayuki ITO Yoshikazu KIYOSHIGE Yusuke NITTA Makoto ISHIKAWA Tetsuya YAMADA Junichi MIYAKOSHI Yasutaka WADA Keiji KIMURA Hironori KASAHARA Hideo MAEJIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4  pp. 663-669
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
heterogeneousinstruction setMMU
 Summary | Full Text:PDF(2.7MB)

Power-Aware Compiler Controllable Chip Multiprocessor
Hiroaki SHIKANO Jun SHIRAKO Yasutaka WADA Keiji KIMURA Hironori KASAHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 432-439
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
chip multiprocessorparallelizing compilerfrequency and voltage control
 Summary | Full Text:PDF(852.3KB)