Yasushi NAITO


Leakage Current Reduction in Surrounding Hi-Capacitor DRAM Cell
Geshu FUSE Ichirou NAKAO Yohei ICHIKAWA Chiaki KUDO Toshiki YABU Akito UNO Kazuyuki SAWADA Yasushi NAITO Michihiro INOUE Hiroshi IWASAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1991/04/25
Vol. E74-C  No. 4  pp. 812-817
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: DRAM
Keyword: 
 Summary | Full Text:PDF(616.1KB)

Double Self-Aligned Contact Technology for Shielded Bit Line Type Stacked Capacitor Cell of 16 MDRAM
Masanori FUKUMOTO Yasushi NAITO Kazuhiro MATSUYAMA Hisashi OGAWA Koji MATSUOKA Takashi HORI Hiroyuki SAKAI Ichiro NAKAO Hisakazu KOTANI Hiroshi IWASAKI Michihiro INOUE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1991/04/25
Vol. E74-C  No. 4  pp. 818-826
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: DRAM
Keyword: 
 Summary | Full Text:PDF(1MB)