IEICE Trans

Yasunobu NAKASE

On-Chip Single-Inductor Dual-Output DC-DC Boost Converter Having Off-Chip Power Transistor Drive and Micro-Computer Controlled MPPT Modes Yasunobu NAKASE Yasuhiro IDO Tsukasa OISHI Toru SHIMIZU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/11/01 Vol. E96-C No. 11 pp. 1420-1427 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: DC-DC converter, environmental harvesting, MPPT,
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A Wide Range 1.0-3.6 V 200 Mbps, Push-Pull Output Buffer Using Parasitic Bipolar Transistors Takahiro SHIMADA Hiromi NOTANI Yasunobu NAKASE Hiroshi MAKINO Shuhei IWADE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/04/01 Vol. E87-C No. 4 pp. 571-577 Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies) Category: Keyword: low power consumption, I/O, parasitic bipolar transistor, forward bias, driver, level converter,
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A Low-Power Microcontroller with Body-Tied SOI Technology Hisakazu SATO Yasuhiro NUNOMURA Niichi ITOH Koji NII Kanako YOSHIDA Hironobu ITO Jingo NAKANISHI Hidehiro TAKATA Yasunobu NAKASE Hiroshi MAKINO Akira YAMADA Takahiko ARAKAWA Toru SHIMIZU Yuichi HIRANO Takashi IPPOSHI Shuhei IWADE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/04/01 Vol. E87-C No. 4 pp. 563-570 Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies) Category: Keyword: low power, high speed, microcontroller, SOI,
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Selective-Sets Resizable Cache Memory Design for High-Performance and Low-Power CPU Core Takashi KURAFUJI Yasunobu NAKASE Hidehiro TAKATA Yukinaga IMAMURA Rei AKIYAMA Tadao YAMANAKA Atsushi IWABU Shutarou YASUDA Toshitsugu MIWA Yasuhiro NUNOMURA Niichi ITOH Tetsuya KAGEMOTO Nobuharu YOSHIOKA Takeshi SHIBAGAKI Hiroyuki KONDO Masayuki KOYAMA Takahiko ARAKAWA Shuhei IWADE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/04/01 Vol. E87-C No. 4 pp. 535-542 Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies) Category: Keyword: resizable cache, selective-sets, hierarchy SRAM, partial swing,
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Interface Technologies for Memories and ASICs -- Review and Future Direction -- Yasuhiro KONISHI Yasunobu NAKASE Katsushi ASAHINA Makoto TANIGUCHI Michihiro YAMADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/03/25 Vol. E82-C No. 3 pp. 438-447 Type of Manuscript: INVITED PAPER (Special Issue on Ultra-High-Speed IC and LSI Technology) Category: Keyword: IO interface, LVTTL, SSTL, SLDRAM, D-RDRAM, PCI, AGP, GTL, HSTL, LVDS,
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A 250 MHz Dual Port Cursor RAM Using Dynamic Data Alignment Architecture Yasunobu NAKASE Hiroyuki KONO Yoshio MATSUDA Hisanori HAMANO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/11/25 Vol. E81-C No. 11 pp. 1750-1756 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: dual port SRAM, computer graphics, cursor,
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A 300 MHz Dual Port Palette RAM Using Port Swap Architecture Yasunobu NAKASE Koichiro MASHIKO Yoshio MATSUDA Takeshi TOKUDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/09/25 Vol. E81-C No. 9 pp. 1484-1490 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: dual port SRAM, graphics, color palette, small cell size,
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A 286 MHz 64-b Floating Point Multiplier with Enhanced CG Operation Hiroshi MAKINO Hiroaki SUZUKI Hiroyuki MORINAKA Yasunobu NAKASE Koichiro MASHIKO Tadashi SUMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/07/25 Vol. E79-C No. 7 pp. 915-924 Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996)) Category: Logic Keyword:
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A 2.6-ns 64-b Fast and Small CMOS Adder Hiroyuki MORINAKA Hiroshi MAKINO Yasunobu NAKASE Hiroaki SUZUKI Koichiro MASHIKO Tadashi SUMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/04/25 Vol. E79-C No. 4 pp. 530-537 Type of Manuscript: Special Section PAPER (Special Issue on Ultra-High-Speed LSIs) Category: Keyword: addition, carry look-ahead adder, binary look-ahead adder, carry select, modified carry select, CMOS, VLSI,
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A Design of High-Speed 4-2 Compressor for Fast Multiplier Hiroshi MAKINO Hiroaki SUZUKI Hiroyuki MORINAKA Yasunobu NAKASE Hirofumi SHINOHARA Koichiro MASHIKO Tadashi SUMI Yasutaka HORIBA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/04/25 Vol. E79-C No. 4 pp. 538-548 Type of Manuscript: Special Section PAPER (Special Issue on Ultra-High-Speed LSIs) Category: Keyword: 4-2 compressor, multiplier, redundant binary, transmission gate, CMOS circuit,
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